Via density change to improve wafer surface planarity

Details Via density change to improve wafer surface planarity Via density change to improve wafer surface planarity

2011-05-24

2011-05-24

Kik, Phallaka (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Physical design processing

C716S051000, C716S054000, C716S126000, C700S098000, C700S121000

Reexamination Certificate

active

07949981

ABSTRACT:
Changing a via density for viafill vias to improve wafer surface planarity for later photolithography is provided, in one embodiment, by obtaining a circuit design including a plurality of viafill vias having differing via density across the circuit design, each viafill via interconnecting non-functional metal fill shapes in different layers of the circuit design; selecting a region of the circuit design to evaluate using an evaluation window; determining a via density within the evaluation window; and changing a number of viafill vias within the region in the circuit design in response to the via density being different than a threshold via density that is selected such that a coating deposited over the plurality of vias presents a substantially planar surface.

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Kahng et al., “DOE-Based Extraction of CMP, Active and Via Fill Impact on Capacitances,” IEEE Transactions on Semiconductor Manufacturing, vol. 21, No. 1, Feb. 2008, pp. 22-32.
Matsui et al., “Focus Error Reduction by Photo-Resist Planarization in Via-First Dual Damascence Process,” IEEE 0-7803-8752-X, 2005, pp. 162-164.

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