Vector logic techniques for multilevel minimization with...

Details Vector logic techniques for multilevel minimization with... Vector logic techniques for multilevel minimization with...

2007-05-29

2007-05-29

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

10931456

ABSTRACT:
Very complex (multilevel) logical expressions are represented in a vector format. The logic is simplified by identifying opposing couples (a literal and its negation) and replacing symmetrical logic expressions attached to the opposing couples with a single version. Significant simplification of the logic can thus be achieved that is suitable for applications in CAD/CAM and in design and manufacture of integrated circuits. The simplification results in increased reliability, lower cost and faster circuits. Techniques for simplifying circuits with multiple outputs are also described.

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Jaekel et al., “Recognizing Nonseries-Parallel Structures in Multilevel Logic Minization,” IEEE, 1995, pp. 95-101.

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