Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-12-21
2004-03-16
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C703S014000, C714S733000
Reexamination Certificate
active
06708317
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the validation of integrated circuit designs. More particularly, this invention relates to the validation of integrated circuit designs in which part of the design is obscured to maintain its confidentiality.
2. Description of the Prior Art
An important part of the development of a new integrated circuit is the validation of the design for that circuit. This typically takes place before any physical examples of the integrated circuit are produced in an effort to remove errors from the design. Sophisticated computer program tools exist to assist in this validation process.
A typical design validation process will use models of different portions of an integrated circuit design and with these models test that signals are correctly exchanged and processed by the different elements within the integrated circuit as a whole. It will be appreciated that with the increase in system-on-a-chip designs, an integrated circuit may contain different portions provided by different suppliers. As an example, a single integrated circuit may include a microprocessor core provided by a first supplier, a random access memory provided by a second supplier and a number of peripheral devices provided by a third supplier. The designs of many of these portions represent confidential and valuable property. In order to protect this property, it is known to provide obscured models of portions of integrated circuits that can be used in design validation and yet do not reveal valuable information regarding the internal design of that portion.
A problem with obscured models is that it is difficult for someone other than the originator of that model to make any changes to it. This can cause problems as it is desirable that at least some trusted parties other than the originator of the obscured model should be able to slightly alter that model for their own purposes. An example of this is that different users of a microprocessor core represented by an obscure model may wish to provide different sets of scan chains for use in testing that microprocessor core. Whilst one of these scan chains may be a wrapper scan chain provided outside of the microprocessor core, it is likely that further scan chains will be within the interior of the microprocessor core and accordingly will require modification of the obscured model of that microprocessor core if they are to be properly modeled by that obscured model during the validation process.
SUMMARY OF THE INVENTION
Viewed from one aspect the present invention provides a method of validating an integrated circuit design having a plurality of circuit portions including:
(i) a prevalidated circuit portion having an obscured prevalidated circuit portion represented by an obscured prevalidated circuit portion model and a non-obscured prevalidated circuit portion represented by a non-obscured prevalidated circuit portion model, and
(ii) an unvalidated circuit portion represented by an unvalidated circuit portion model, said method comprising the steps of:
(iii) simulating interaction between said unvalidated circuit portion and said non-obscured prevalidated circuit portion using said unvalidated circuit portion model and said non-obscured prevalidated circuit portion model; and
(iv) verifying correct interaction of said unvalidated circuit portion model and said non-obscured prevalidated circuit portion model during said step of simulating interaction between said unvalidated circuit portion and said non-obscured prevalidated circuit portion to validate design of said unvalidated circuit portion in interaction with said non-obscured circuit portion, wherein
(v) said unvalidated circuit portion model does not interact with said obscured prevalidated circuit portion model during said step of simulating interaction between said unvalidated circuit portion and said non-obscured prevalidated circuit portion, and said prevalidated circuit portion includes one or more scan chains, said one or more scan chains being part of said non-obscured circuit portion and modeled by said non-obscured prevalidated circuit portion model.
The invention recognizes that whilst a prevalidated circuit portion, such as a microprocessor core and its associated scan chains, that is provided on a general basis should preserve the confidentiality of the important information, it is possible to segment the model provided into an obscured part and a non-obscured part. The obscured part can be provided by the originator of the valuable design and the non-obscured part, for example, provided by the originator or by trusted parties to model those portions of the pre-validated circuit portion over which it is desired to give those trusted parties some control. This prevalidated model having obscured and non-obscured portions that is then released to, for example, a system-on-a-chip provider enables validation of the circuits produced by that system-on-a-chip provider to be carried out using a prevalidated model for a portion of that design and maintains the confidentiality of the crucial design information whilst allowing a degree of flexibility in the design of the prevalidated portion without requiring a completely new obscured model to be generated.
As a specific example, a microprocessor core design may be represented by an obscured model. This design may be released to trusted parties who customize the design to a form in which it can be manufactured by their particular manufacturing processes and which will have its own set of most appropriate scan chains. When this microprocessor core and associated scan chains are included within a larger system-on-a-chip design, it is important that the complete design including interaction with both the microprocessor core represented by the obscured model and the scan chains associated with the non-obscured model are properly validated. A mistake in the way the system-on-a-chip integrated circuit is produced associated with the operation of the scan chains may be just as difficult and expensive to rectify as one associated with the operation of a microprocessor core. However, providing a non-obscured model of the scan chains allows these to be validated as part of the design without revealing valuable confidential information regarding the interior of the microprocessor core that is represented by the difficult to produce and tightly controlled obscured model.
It will be appreciated that whilst the above specific example refers to microprocessor cores and scan chains (both wrapper scan chains and internal scan chains), the invention may also be used for different circuit portions within an integrated circuit design. For example, the logic for a custom functional block (such as a coprocessor) that is added by a trusted party to an existing processor.
Viewed from another aspect the present invention also provides a model for a prevalidated portion of an integrated circuit having an obscured prevalidated circuit portion and a non-obscured prevalidated circuit portion, said model comprising:
(i) an obscured prevalidated circuit portion model representing said obscured prevalidated circuit portion; and
(ii) a non-obscured prevalidated circuit portion model representing said non-obscured prevalidated circuit portion, wherein
(iii) said prevalidated circuit portion includes one or more scan chains, said one or more scan chains being part of said non-obscured circuit portion and modeled by said non-obscured prevalidated circuit portion model.
Viewed from a further aspect the invention also provides a method of producing a model of a prevalidated portion of an integrated circuit having an obscured prevalidated circuit portion and a non-obscured prevalidated circuit portion, said method comprising the steps of:
(i) providing an obscured prevalidated circuit portion model representing said obscured prevalidated circuit portion;
(ii) generating a representation of said prevalidated circuit portion including both said obscured prevalidated circuit portion and said non-obscured prevalidated circuit por
ARM Limited
Dimyan Magid Y
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