Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-01-03
2003-02-04
Niebling, John F. (Department: 2812)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06516450
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the design and manufacture of integrated circuits (ICs) or semiconductor devices. More particularly, the present invention relates to an apparatus for and a method of determining design rule parameters for semiconductor wafers or integrated circuits.
BACKGROUND OF THE INVENTION
Integrated circuits are manufactured on semiconductor wafers according to design rules. Design rules typically relate to parameters associated with the manufacture of the integrated circuit. Design rules can specify the fabrication constraints associated with the manufacture of a device. For example, design rules can relate to various lithographic tolerances between structures on a semiconductor device, feature sizes, layer thickness, implant dosages, element dimensions or other criteria. The design rules can generally mandate the minimum feature size, overlap requirements, separation (spacing) requirements, or other parameters necessary to ensure that a fabricated device operates properly.
The design rules which proscribe IC design must be proven. Typically, a set of design rules are proven by fabricating an IC designed according to a design rule set and assuring proper operation of the fabricated IC. The efficacy of the design rules are presumed when the fabricated IC is shown to be functional.
For example, design rules for an IC used in amplifier circuits have been tested by providing power devices on a wafer. The power devices are built according to design rule parameters which are deliberately adjusted or offset. After manufacture, the power devices are tested to determine at which point the structure failed. Specifically, in an IC including doubly diffused metal oxide semiconductor (DMOS), a plurality of power devices are arranged in an array. Design rule parameters are adjusted or offset for each power device in the array. After the wafer is manufactured, the power devices are tested to determine which power devices failed. Analysis of failing power devices demonstrates the point of offset at which failure occurred. Thus, design rules associated with operable power devices are proven.
According to another example, design rules can be proven by providing a large semiconductor memory on a wafer. Each memory unit is identical and manufactured in accordance with fixed design rules. If the semiconductor wafer memory operates properly, the entire set of design rules is considered appropriate. This type of testing is more effective for uncovering random process errors rather than design rule tolerances.
If the memory does not operate properly, the memory is manually analyzed to determine the reason for the failure. For example, the wafer can be viewed through a microscope, a scanning electron microscope (SEM), or KLA inspection tool to determine the reason for the device failure. Alternatively, electrical testing or other diagnostic tools can determine the reason for the device failure. Manual analysis is time consuming and difficult, particularly when a large number of the design rules can cause the failure.
While the preceding methods for proving design rules are effective, they require iterations of design and fabrication as well as complicated manual analysis. Thus, there is a need for a variable design rule tool which allows a set of design rules to be tested quickly. Further still, there is a need for a method of and apparatus for testing a number of design rules automatically and simultaneously. Even further still, there is a need for a tool which can isolate design rule parameters which cause semiconductor processing failures.
SUMMARY OF THE INVENTION
One exemplary embodiment relates to a variable design rule tool. The design rule tool includes a matrix of units having a plurality of rows and columns. The matrix is disposed on a semiconductor substrate. The units in a particular row are associated with a particular semiconductor fabrication design rule; a parameter associated with the semiconductor fabrication design rule decreasing in tolerance from one end to the opposite end of the particular row or column. The variable design rule tool also includes an interface coupled to the matrix and a program. The interface receives data associated with the units. The program receives the data from the interface and determines a failure point associated with the parameter in response to the data.
Another embodiment relates to a wafer for use in a design test for a semiconductor fabrication system. The design test determines a particular value for a parameter associated with a device failure on a wafer. The wafer includes a plurality of memory units, each being associated with a selected value for the parameter. The design test allows the particular value to be determined in response to data associated with the units.
Yet another exemplary embodiment relates to a method of testing a design rule for an integrated circuit. The integrated circuit includes a plurality of memory units. The units are arranged in a plurality of rows and a plurality of columns. The units in a particular row or particular column are associated with a particular design rule. A parameter associated with a design rule varies from a first end to a second end of the particular row or column. The method includes providing data to the units, receiving the data from the units, analyzing the data to determine if a unit has failed, and determining the parameter associated with the failed unit.
REFERENCES:
patent: 5559997 (1996-09-01), Tsuchida et al.
patent: 5681674 (1997-10-01), Fujimoto
patent: 6063132 (2000-05-01), DeCamp et al.
Dekker, R. et al., “A realistic fault model and test algorithms for SRAM's”, Jun. 1990. IEEE, pp. 567-572.*
Ilyoung, Kim et al., “Built in self repair for embedded high density SRAM”, Oct. 1998. IEEE, pp. 1112-1119.*
Rajsuman, “An algorithm and design to test RAM's”, May 1992. IEEE, pp. 439-442.
Hang Rithy
Hill Wiley Eugene
Lee Chern-Jiann
Lukanc Todd
Taylor Kurt
Advanced Micro Devices , Inc.
Niebling John F.
Whitmore Stacy
LandOfFree
Variable design rule tool does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Variable design rule tool, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Variable design rule tool will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3126901