Variable detail automatic invocation of transistor level...

Details Variable detail automatic invocation of transistor level... Variable detail automatic invocation of transistor level...

2001-08-16

2004-12-07

Garbowski, Leigh M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C703S019000

Reexamination Certificate

active

06829755

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to design tools used in development of application specific integrated circuit (ASIC) technology; and more particularly to techniques for performing timing analysis on circuit designs used in ASICs.
2. Description of the Related Art
Present electronic designing systems consist of software tools running on a digital computer that assist a designer in the creation and verification of complex electronic designs. Electronic computer-aided design (ECAD) systems are widely used in designing semiconductor integrated circuits. In particular, ECAD systems are used to generate data descriptive of the entire circuit layout as well as the layout of individual circuit cells. Since each cell often contains a large number of circuit elements and interconnections among the elements and their respective timing, ECAD systems have become an indispensable tool in the design of integrated circuits.
In the process of creating a large integrated circuit chip design, it is quite useful and customary to partition the logic into manageable pieces and to design hierarchically. This modularity maximizes reuse and simplifies the design. Some of the design pieces or blocks might be custom designed, while others could simply be synthesized ASIC blocks. If the design is to be processed by a timing analysis tool, such as a static timing analyzer, there must at least be timing information for each of the lowest level building blocks of the design. Timing information about these blocks is presented to the timing analysis tool in the form of timing rules.
There currently exist static timing analysis tools, which are commonly made available by vendors of ECAD stations and software, for timing analysis. Timing analysis is performed by software which analyzes the timing relationships between logic state changes within a circuit and determines if certain timing criteria such as minimum setup and hold times have been violated. A static timing analyzer does not attempt to model the circuit as it would operate but rather attempts to analyze a circuit's temporal behavior.
ASIC level static timing analysis requires use of a “netlist” describing the ASIC circuit to be timed, and timing rules. The netlist is a compilation of information descriptive of the primitives (i.e., circuit elements) of a logic circuit. Netlist can also be a cell description (a group of circuit elements) and their interconnection. The timing rules specify the timing for these circuits. Development and verification tools used in ASIC design usually implement a hardware description language. Static timing analysis use a number of industry standard formats for such netlists that include the Netlist Description Format (NDL), the Electronic Data Interchange Format (EDIF), etc. These netlist comprises a list of basic cells used in the design of the system, specifying interconnection among the cells. Connections between or among cells are known as nets. A circuit path through a system comprises a number of cells and the interconnecting nets for the circuit path. In most situations, this modeling provides adequate results, and the circuit can be timed reasonably well. However, a certain class of circuits having “open channel inputs” cannot be timed adequately using present forms of this analysis. Typically in complementary metal oxide semiconductor CMOS based logic circuits, the input pin(s) of a cell is connected to the GATE of a CMOS transistor. An “open channel input” cell refers to a cell where the input pin(s) are connected to the source or drain of a CMOS transistor. In particular, using these conventional timing analytical frameworks for timing results, the load capacitance of each input pin on a particular circuit must be fixed. However, when a circuit has an open channel input, the load capacitance can have many different values. In some pathological situations, the load capacitance measured at the input to a circuit is not a function of that circuit. Instead, it is a function of that circuit and its electrical neighbors and interconnect connecting the circuit to its neighbors, commonly referred to as a static channel connected component (CCC).
To resolve such problems, a static-timing-analysis subsystem called transistor level timing (TLT) is used for timing such “open channel input” circuits. Since TLT disregards gate boundaries, “open channel input” problems do not exist. When TLT partitions a transistor circuit to analyze, this methodology divides the circuit so that no “open channel inputs” in the resulting partition exist.
FIG. 1
shows a conventional method of ASIC timing wherein a netlist is provided to a timer for generating a timing report from timing graphs using timing rules, capacitive parasitics and assertions. A NETLIST is an explicit list of cells and their interconnection. A TIMING RULE is a set of data and algorithms which specify the temporal behavior of a particular type of gate under different conditions, such as temperature, voltage, capacitive loading of signal outputs, and rate-of-change (slew) of signal input voltages. PARASITICS specify the electrical characteristics of the interconnections in the netlist, especially the resistance and capacitance. ASSERTIONS specify externally imposed timing constraints of the netlist. Conventional timing graphs for this method are shown in
FIGS. 2
a
-
2
d
as to how these timing graphs are constructed in association with an “open channel input” problem.
Referring now to
FIG. 1
, the conventional timing processes is represented in a block diagram. Item
10
of the block diagram is the net list. An example of a net list is shown in
FIG. 2
a
, discussed below. Item
208
illustrates timing rules that the net list
10
must comply with. Exemplary timing rules are shown in
FIGS. 2
c
and
2
d
, discussed below. Additional variables such as parasitic capacitance
70
and assertions
60
are also shown in FIG.
1
. Item
60
of this figure represent the external temporal requirements imposed on the netlist under analysis. These ASSERTIONS might include arrival times at the primary inputs to the netlist, and the arrival times required at the primary outputs of the netlist. In an item
100
, these conventional systems build a timing graph with the information from the netlists
10
and the timing rules
208
. An example of a timing graph is shown in
FIG. 2
b
, discussed below. In item
90
, the timing graph is annotated with the delays, arrival times and required arrival times using the information from the assertions
6
, the parasitics
70
, the timing graph and the timing rules
208
.
In addition, the conventional process generates timing reports for the user using the timing graph and the netlist
10
. A timing report is a text or graphical based summary of the temporal behavior of the netlist. This report may include the delay of the longest path through the netlist, an annotated list of the cells (and their individual delays) in the longest path, and the results of timing tests within the netlist and timing tests at the primary inputs and outputs of the netlist. The intent of the timing report is to concisely represent the critical timing(s) within the netlist, and alert the circuit designer to potential situations within the netlist that would prevent the proper operation of the netlist.
As mentioned above
FIG. 2
a
illustrate a net list
200
that includes a first item
202
that is a box having a name A representing an inverter. Box
204
which has a name B and is a latch. The boxes are connected by a net
206
named C. The timing graph shown in
FIG. 2
b
illustrates the input
210
to box A
202
and the output from box A
212
. Once again the net
206
connecting the boxes
202
,
204
is also shown in
FIG. 2
b.
The data
214
and clock
216
inputs into box
204
and the output
218
from box
204
are also illustrated in
FIG. 2
b.
FIG. 2
c
illustrates the timing rules for the inverter shown in box
202
. Equation 2 in
FIG. 2
c
represents a possible function for calculating the dela

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