Variable stage ratio buffer insertion for noise optimization...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000

Reexamination Certificate

active

06990647

ABSTRACT:
A buffer for use in a logic circuit comprises input and output nodes. A first inverter having a first device size is coupled to the input node. A second inverter is coupled in series with the first inverter and with the output node. The second inverter having a second device size at least six times greater than the first device size. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).

REFERENCES:
patent: 5847966 (1998-12-01), Uchino et al.
patent: 5986463 (1999-11-01), Takiguchi
patent: 6117182 (2000-09-01), Alpert et al.
patent: 6252418 (2001-06-01), Durham et al.
patent: 6351179 (2002-02-01), Ikehashi et al.
patent: 2002/0188892 (2002-12-01), Lajolo
patent: 2003/0117183 (2003-06-01), Thibeault et al.
“What is the Appropriate Model for Crosstalk Control?,” Lou Sheffer, Cadence Design Systems, 2000 IEEE, pp. 315-320.
“Buffer Insertion for Noise and Delay Optimization,” Charles Alpert, et al., IEEE Transactions on Computer-Aided Design on Integrated Circuits and Systems, vol. 18 No. 11, Nov. 1999, pp. 1633-1645.

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