Vector Logic techniques for multilevel minimization

Details Vector Logic techniques for multilevel minimization Vector Logic techniques for multilevel minimization

2007-02-06

2007-02-06

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

10655766

ABSTRACT:
Very complex (multilevel) logical expressions are represented in a vector format. The logic is simplified by identifying opposing couples (a literal and its negation) and replacing symmetrical logic expressions attached to the opposing couples with a single version. Significant simplification of the logic can thus be achieved that is suitable for applications in CAD/CAM and in design and manufacture of integrated circuits. The simplification results in increased reliability, lower cost and faster circuits.

REFERENCES:
patent: 4816999 (1989-03-01), Berman et al.
patent: 5047969 (1991-09-01), Sloane
patent: 5128871 (1992-07-01), Schmitz
patent: 5493504 (1996-02-01), Minato
patent: 5862149 (1999-01-01), Carpenter et al.
patent: 5867397 (1999-02-01), Koza et al.
patent: 6175949 (2001-01-01), Gristede et al.
patent: 6336208 (2002-01-01), Mohan et al.
patent: 6499129 (2002-12-01), Srinivasan et al.
patent: 6851095 (2005-02-01), Srinivasan et al.
Scholl et al., “BDD Minimization Using Symmetries,” IEEE, Feb. 1999, pp. 81-100.
School et al., “Minimizing ROBDD Size of Incompletely Specified Boolean Fuctions by Exploiting Strong Symmetries,” IEEE, 1997, pp. 229-234.
Jaekel et al., “Recognizing Nonseries-Parallel Structures in Mjltilevel Logic Minimization,” IEEE, 1995, pp. 95-101.

Affiliated with

Also associated with

Rating

Vector Logic techniques for multilevel minimization does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Vector Logic techniques for multilevel minimization, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Vector Logic techniques for multilevel minimization will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3827421