Variable clocked scan test improvements

Details Variable clocked scan test improvements Variable clocked scan test improvements

2008-04-01

2008-04-01

Lin, Sun James (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07353470

ABSTRACT:
Addition of specific test logic may improve the level of test vector compression achieved from existing variable scan test logic. Methods for determining the compressed vectors' states, given the desired uncompressed vectors' values may be used, and techniques for selectively enabling test or other features on a chip by inserting the proper code or codes into the chip may further be used. Techniques may be used to incorporate and apply various types of reset operations to multiple strings of variable scan test logic, as may methods to minimize the test vector compression computation time.

REFERENCES:
patent: 5968141 (1999-10-01), Tsai
patent: 5991909 (1999-11-01), Rajski et al.
patent: 7111209 (2006-09-01), Rajski et al.
patent: 7234092 (2007-06-01), Cooke
patent: 2003/0229834 (2003-12-01), Cooke
patent: 2005/0140773 (2005-06-01), O'Hara et al.

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