CMOS integrated circuits including source/drain plug

CMOS integrated microsensor with a precision measurement circuit

CMOS interface circuit formed in silicon-on-insulator substrate

CMOS inverter constructions

CMOS inverter coupling circuit comprising vertical transistors

CMOS inverter using gate induced drain leakage current

CMOS inverters configured using multiple-gate transistors

CMOS latchup suppression by localized minority carrier lifetime

CMOS locos isolation for self-aligned NPN BJT in a BiCMOS proces

CMOS logic gate fabricated on hybrid crystal orientations...

CMOS logic gate having buried channel NMOS transistor for semico

CMOS master slice

CMOS memory device with improved sense amplifier biasing

CMOS of semiconductor device and method for manufacturing...

CMOS on hybrid substrate with different crystal orientations...

CMOS on hybrid substrate with different crystal orientations...

CMOS OP-AMP circuit using BJT as input stage

CMOS output buffer with enhanced ESD resistance

CMOS output circuit with enhanced ESD protection using drain...

CMOS performance enhancement using localized voids and...