CMOS output circuit with enhanced ESD protection using drain...

Details CMOS output circuit with enhanced ESD protection using drain... CMOS output circuit with enhanced ESD protection using drain...

2002-08-07

2003-11-25

Wojciechowicz, Edward (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

C257S355000, C257S356000, C257S357000, C257S359000, C257S360000, C257S361000, C257S362000

Reexamination Certificate

active

06653709

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a device and a method of fabrication thereof for electrostatic discharge (ESD) protection, and more particularly, to a novel output circuit for use in a CMOS integrated circuit device.
(2) Description of the Prior Art
As device dimensions continue to be reduced, susceptibility to electrostatic discharge (ESD) damage is a growing concern. ESD events occur when charge is transferred between one or more pins of an integrated circuit and another conducting object in a short period of time, typically less than one microsecond. The rapid charge transfer generates voltages large enough to breakdown insulating films, such as silicon dioxide, and to cause permanent damage to the device. To deal with the problem of ESD events, integrated circuit manufactures have designed various structures on the input and output pins of their devices to shunt ESD currents away from sensitive internal structures.
Referring now to
FIG. 1
, a prior art CMOS output circuit is illustrated. In this circuit, an internal circuit voltage, SIGNAL
20
, is propagated to an output pin, PAD
24
. A driver stage inverter is made up of NMOS transistor N
1
8
and PMOS transistor P
1
4
. The output of the driver stage is tied directly to the output PAD
24
. In addition, two protection devices, N
2
and P
2
, are used in a dummy stage. An NMOS device, N
2
16
, and a PMOS device P
2
12
, are each connected with zero gate bias such that each device is OFF during normal operating conditions. However, if a negative voltage spike occurs at PAD
24
, then the dummy stage protection devices turn ON and shunt current to either ground
28
or to the supply voltage (VCC)
32
. In addition, if a large positive voltage spike occurs at PAD
24
, then the diodes formed by the drain to substrate junctions of N
2
and P
2
will forward bias and provide a current shunt.
Referring now to
FIG. 2
, a cross sectional view of an integrated circuit incorporating a portion of the circuit is shown. The two NMOS devices, N
1
and N
2
, are formed. Gates for N
1
60
and for N
2
64
are formed by patterning a polysilicon layer overlying silicon dioxide
72
. The gates
60
and
64
overlie the semiconductor substrate
40
to form a channel region for each transistor. The drain and source regions comprise the n+ implanted areas
44
,
48
, and
52
. Silicide
56
may be formed in the drain and source prior to deposition of the metal layer
68
. Note that a p− region
76
is implanted under both the source
44
and
52
and drain
48
regions of both devices.
Referring again to
FIG. 1
, a problem with the prior art device is that the voltage at the output PAD must be kept very low. This is because the entire voltage differential between PAD
24
and ground
28
is across the gate dielectric of the NMOS device N
2
16
. In devices with gate lengths of about 0.18 microns, it is found that the very thin gate oxide used can breakdown at about 5 Volts. This can limit the application of these integrated circuit devices.
Several prior art inventions describe ESD devices and circuits. U.S. Pat. No. 5,898,205 to Lee teaches an ESD protection circuit where conventional CMOS protection transistors are capacitively-coupled to improve performance. U.S. Pat. No. 6,066,879 to Lee et al discloses a method to form an ESD device where a SCR protection device and an NMOS or DENMOS transistor are integrated. U.S. Pat. No. 5,870,268 to Lin et al teaches a transient switching circuit that forward biases a n+/p-well diode to cause minority carrier injection into the substrate. U.S. Pat. No. 5,559,352 to Hsue et al teaches a method to form an ESD device with a reduced breakdown voltage. A deep ion implantation is performed in both the source and drain regions to reduce the breakdown voltage.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable output circuit that protects a CMOS integrated circuit from electrostatic discharge (ESD) events.
A further object of the present invention is to provide an output circuit that can withstand larger dc voltages on the output pin by cascading NMOS transistors.
A still further object of the present invention is to provide an output circuit with cascaded NMOS transistors and with enhanced ESD performance through the use of a p-implanted region under the drain.
Another object of the present invention is to provide an effective and very manufacturable method to fabricate a cascaded NMOS transistor output circuit with enhanced ESD performance in a CMOS integrated circuit device.
In accordance with the objects of this invention, a new cascaded NMOS transistor output circuit with enhanced ESD protection is achieved. A driver PMOS transistor has the source connected to a voltage supply, the gate connected to the input signal, and the drain connected to the output pad. A dummy PMOS transistor has the source and the gate connected to the voltage supply, and the drain connected to the output pad. A driver NMOS cascaded stack comprises first and second NMOS transistors. The first NMOS transistor has the source connected to ground and the gate connected to the input signal. The second NMOS transistor has the gate connected to the voltage supply, the source connected to the first NMOS transistor drain, and the drain connected to the output pad. A p− implanted region underlies the n+ region of the drain but does not underlie the n+ region of the source. A dummy NMOS cascaded stack comprises third and fourth NMOS transistors. The third NMOS transistor has the gate and the source connected to ground. The fourth NMOS transistor has the gate connected to the voltage supply, the source connected to the third MOS transistor drain, and the drain connected to the output pad. A p− implanted region underlies the n+ region of the drain but does not underlie the n+ region of the source.
Also in accordance with the objects of this invention, a method to fabricate a cascaded NMOS transistor output circuit with enhanced ESD protection is achieved. N-type regions and p-type regions are provided in a semiconductor substrate. A gate oxide layer is formed overlying the semiconductor substrate. A polysilicon layer is deposited overlying said gate oxide layer. The polysilicon layer is patterned to form transistor gates for NMOS and PMOS output transistors. Ions are implanted into the semiconductor substrate to form n+ regions for NMOS output transistor drains and sources and to form p+ regions for PMOS output transistor drains and sources. Ions are implanted into the semiconductor substrate to form p− implanted regions underlying the n+ regions of the NMOS output transistor drains. The implanting is selective to only the NMOS output transistor drains connected to planned output pads. An interlevel dielectric layer is deposited overlying the NMOS and PMOS output transistors. The interlevel dielectric layer is patterned to form contact openings. A metal layer is deposited overlying the interlevel dielectric layer and filling the contact openings. The metal layer is patterned to complete the NMOS and PMOS output transistors in the manufacture of the integrated circuit device.


REFERENCES:
patent: 5986867 (1999-11-01), Duvvury et al.

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