CMOS output buffer with enhanced ESD resistance

Details CMOS output buffer with enhanced ESD resistance CMOS output buffer with enhanced ESD resistance

1994-09-30

1996-05-14

Jackson, Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257345, 257369, 257392, H01L 27092, H01L 218238

Patent

active

055170498

ABSTRACT:
The present invention provides a CMOS integrated circuit in which core transistors are provided with punch-through pockets, while the input/output transistors are not provided with punch-through pockets. Punch-through protection for the input/output transistors by virtue of their larger dimensions. The pockets, like lightly doped drains, are formed after the gates are formed but before the formation of gate sidewalls. However, the input/output are masked during the punch-through implants, but are unmasked for at least one of the lightly doped drain implants. The absence of pockets on the input/output transistors enhances their ESD resistance, and thus the ESD resistance of the incorporating integrated circuit.

REFERENCES:
patent: 4894694 (1990-01-01), Cham et al.

Affiliated with

Also associated with

Rating

CMOS output buffer with enhanced ESD resistance does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with CMOS output buffer with enhanced ESD resistance, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and CMOS output buffer with enhanced ESD resistance will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1898035