CMOS locos isolation for self-aligned NPN BJT in a BiCMOS proces

Details CMOS locos isolation for self-aligned NPN BJT in a BiCMOS proces CMOS locos isolation for self-aligned NPN BJT in a BiCMOS proces

1994-08-24

1996-04-02

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257377, 257 51, 257506, 257518, 257519, 257588, 257592, 437 31, 437 34, 437 57, 437 63, 437186, 437233, H01L 2702, H01L 21265

Patent

active

055043640

ABSTRACT:
A method of fabricating BiCMOS devices, and the resultant BiCMOS device, are disclosed. According to the present invention, over-etching to the substrate on the deposited polysilicon emitter is prevented by providing additional oxide beneath a polysilicon layer as an etch stop. Despite inclusion of an oxide to define an end-point during patterning of an emitter, fabrication complexity is reduced by avoiding additional SAT masking and oxidation steps.

REFERENCES:
patent: 4727046 (1988-02-01), Tuntasood et al.
patent: 4912055 (1990-03-01), Min et al.
patent: 4987093 (1991-01-01), Teng et al.
patent: 5023192 (1991-06-01), Josquin et al.
patent: 5023193 (1991-06-01), Manoliu et al.
patent: 5034351 (1991-07-01), Sun et al.
Chen et al., An Advanced Bipolar Transistor with Self-Aligned Ion-Implanted Base and W/Poly Emitter, IEEE Transactions on Electron Devices, vol. 35(8); pp. 1322-1327, Aug. 1988.

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