CMOS performance enhancement using localized voids and...

Details CMOS performance enhancement using localized voids and... CMOS performance enhancement using localized voids and...

2005-04-12

2005-04-12

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

Having specific type of active device

C257S351000, C257S616000, C438S199000, C438S301000

Reexamination Certificate

active

06878978

ABSTRACT:
The speed of CMOS circuits is improved by imposing a longitudinal tensile stress on the NFETs and a longitudinal compressive stress on the PFETS, by implanting in the sources and drains of the NFETs ions from the eighth column of the periodic table and hydrogen and implanting in the sources and drains of the PFETs ions from the fourth and sixth columns of the periodic table.

REFERENCES:
patent: 6057581 (2000-05-01), Doan
patent: 6075262 (2000-06-01), Moriuchi et al.
patent: 6258695 (2001-07-01), Dunn et al.
patent: 6740913 (2004-05-01), Doyle et al.
patent: 20030040158 (2003-02-01), Saitoh

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