CMOS logic gate fabricated on hybrid crystal orientations...

Details CMOS logic gate fabricated on hybrid crystal orientations... CMOS logic gate fabricated on hybrid crystal orientations...

2007-04-24

2007-04-24

Huynh, Andy (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Physical configuration of semiconductor

With specified crystal plane or axis

C257S347000, C257S371000, C257S527000, C257SE27112

Reexamination Certificate

active

10989080

ABSTRACT:
In preferred embodiments of the present invention, a method of forming CMOS devices using SOI and hybrid substrate orientations is described. In accordance with a preferred embodiment, a substrate may have multiple crystal orientations. One logic gate in the substrate may comprise at least one N-FET on one crystal orientation and at least one P-FET on another crystal orientation. Another logic gate in the substrate may comprise at least one N-FET and at least one P-FET on the same orientation. Alternative embodiments further include determining the preferred cleavage planes of the substrates and orienting the substrates relative to each other in view of their respective preferred cleavage planes. In a preferred embodiment, the cleavage planes are not parallel.

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