CMOS master slice

Details CMOS master slice CMOS master slice

1991-08-09

1993-02-16

Wojciechowicz, Edward J.

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

Having specific type of active device

H01L 2702

Patent

active

051875560

ABSTRACT:
A CMOS master slice having a plurality of regularly arranged basic cells improves an integration efficiency by optimizing size and arrangement of MOS transistors in the basic cells. Each of the basic cells comprises a first pair of transistors having gates thereof arranged to parallelly face each other, and a second pair of transistors having gate electrodes shorter in gate width than that of the first pair of transistors and parallel to the gate electrodes of the first pair of transistors. In adjacent basic cells, the gate electrodes of adjacent second transistors are substantially on a line so that a wasteful space is eliminated.

REFERENCES:
patent: 5038192 (1991-08-01), Bonneau et al.
patent: 5060046 (1991-10-01), Shintani
IBM Technical Disclosure Bulletin, vol. 32, No. 88, Jan. 1990, p. 37.
Patent Abstracts of Japan, vol. 7, No. 52 (E-162) [1197], Mar. 2, 1983, JP-A-57 201060.
Patent Abstracts of Japan, vol. 14, No. 448 (E-983), Sep. 26, 1990, JP-A-2-177456.

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