Integrated circuit cell architecture and routing scheme
Integrated circuit cell architecture configurable for memory...
Integrated circuit device and associated layout including...
Integrated circuit device and associated layout including...
Integrated circuit having gates and active regions forming a...
Integrated circuit having gates and active regions forming a...
Integrated circuit having memory cells and method of...
Integrated circuit incorporating decoupling capacitor under...
Integrated circuit with reduced analog coupling noise
Integrated circuit with reduced analog coupling noise
Integrated CMOS gate-array circuit
Layout method of semiconductor device
Layout of butting contacts of a semiconductor device
Layout pattern of memory cell circuit
Layout structure of multiplexer cells
LDMOS transistor structure using a drain ring with a...
Low dielectric constant sidewall spacer using notch gate...
Master slice type integrated circuit system having block areas o
Master-slice type semiconductor device
Memory cell configuration and corresponding production process