Layout of butting contacts of a semiconductor device

Details Layout of butting contacts of a semiconductor device Layout of butting contacts of a semiconductor device

1996-07-03

1998-05-19

Thomas, Tom

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

Having specific type of active device

257343, 257369, 257372, 257773, H01L 27105

Patent

active

057539448

ABSTRACT:
A semiconductor device having a butting-contact structure for stabilized contact resistance is disclosed. The semiconductor device includes, in the same number, PN regions each having a source region and a diffusion layer in the order with respect to a Y-axis positive direction and PN regions each having a source region and a diffusion layer placed reverse thereto. MOSFET elements have an identical shape in their PN contacts. The interval of the PN contacts is determined equivalent to the interval of boundary lines of the ON regions. The PN contacts are provided such that their centers substantially align with respective boundary lines of the PN regions. Therefore, even when deviation occurs between the PN region and the PN contact along the Y-axis direction, there is provided a equivalency between the sum of areas of the source contact and the sum of areas of the diffusion layer contacts throughout the device.

REFERENCES:
patent: 5404034 (1995-04-01), Yin

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