Integrated CMOS gate-array circuit

Details Integrated CMOS gate-array circuit Integrated CMOS gate-array circuit

1991-12-05

1993-10-05

Hille, Rolf

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

Having specific type of active device

257204, 257369, H01L 27104, H01L 2976

Patent

active

052508234

ABSTRACT:
A gate array circuit includes a row of consecutively arranged n-channel transistors and an adjacent row of p-channel transistors. Both rows are composed of at least three subrows with two subrows of narrow transistors and one subrow of wide transistors, of which the channel width is at least three times the width of the narrow transistors. The gate electrodes are common to the three subrows. Preferably, the wide subrow is arranged centrally between the narrow subrows. This construction affords the advantage of a very high density and a very high flexibility in designing the functions to be realized.

REFERENCES:
patent: 4623911 (1986-11-01), Pryor
patent: 4644187 (1987-02-01), Haji
patent: 4716308 (1987-12-01), Matsuo et al.
patent: 4764798 (1988-08-01), Kawabata
patent: 4825273 (1989-04-01), Arakawa
patent: 5038192 (1991-08-01), Bonneau
patent: 5107147 (1992-04-01), Yee et al.

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