Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – Having specific type of active device
Patent
1997-05-09
1999-04-27
Thomas, Tom
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
Having specific type of active device
257204, 257211, 257758, 438622, 438623, 438624, 438625, H01L 2710
Patent
active
058981942
ABSTRACT:
A CMOS cell architecture and routing technique is optimized for three or more interconnect layer cell based integrated circuits such as gate arrays. First and second layer interconnect lines are disposed in parallel and are used as both global interconnect lines and interconnect lines internal to the cells. Third layer interconnect lines extend transverse to the first two layer interconnects and can freely cross over the cells. Non-rectangular diffusion regions, shared gate electrodes, judicious placement of substrate contact regions, and the provision for an additional small transistor for specific applications are among numerous novel layout techniques that yield various embodiments for a highly compact and flexible cell architecture. The overall result is significant reduction in the size of the basic cell, lower power dissipation, reduced wire trace impedances, and reduced noise.
REFERENCES:
patent: 4611236 (1986-09-01), Sato
patent: 4649294 (1987-03-01), McLaughlin
patent: 4668972 (1987-05-01), Sato et al.
patent: 4682201 (1987-07-01), Lipp
patent: 4727266 (1988-02-01), Fujii et al.
patent: 4804868 (1989-02-01), Masuda et al.
patent: 4816887 (1989-03-01), Sato
patent: 4884118 (1989-11-01), Hui et al.
patent: 5038192 (1991-08-01), Bonneau et al.
patent: 5079614 (1992-01-01), Khatakhotan
patent: 5341041 (1994-08-01), El Gamal
patent: 5723883 (1998-03-01), Gheewala
A. Hui et al., A 4.1 Gates Double Metal HCMOS Sea of Gates Array, IEEE 1985 Custom Integrated Circuits Conference, CH2157-6/85/0000-0015.
A. El Gamal et al., BiNMOS: A Basic Cell for BiCMOS Sea-of-Gates, IEEE 1989 Custom Integrated Circuits Conference, paper No. 8.3.1.
C. Yao et al., An Efficient Power Routing Technique to Resolve the Current Crowding Effect in the Power Grid Structure of Gate Arrays, IEEE 1994 7th Annual ASIC Conference, Rochester, 0-7803-2020-4/94.
Y. Okuno et al., 0.8 um 1.4MTr. CMOS SOG Based on Column Macro-cell, IEEE 1989 Custom Integrated Circuits Conference, CH2671-6/89/0000-0036.
Abraham Fetsum
In-Chip Systems, Inc.
Thomas Tom
LandOfFree
Integrated circuit cell architecture and routing scheme does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuit cell architecture and routing scheme, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit cell architecture and routing scheme will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-686802