Layout structure of multiplexer cells

Details Layout structure of multiplexer cells Layout structure of multiplexer cells

2005-04-26

2005-04-26

Elms, Richard (Department: 2824)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

Having specific type of active device

C257S208000, C257S210000, C257S211000, C257S369000, C257S371000

Reexamination Certificate

active

06885045

ABSTRACT:
A multiplexer cell layout structure is a layout structure of primitive cells where cell arrays composed of P-channel transistors and N-channel transistors are arranged in two upper and lower rows. And, a plurality of transistors of transfer gates are arranged on the upper side and lower side of the cell arrays, an output terminal of the plurality of arranged transistors is connected up and down by Metal wiring across between the upper and lower cell arrays. Thus, a multiplexer cell layout structure which increases wiring tracks of two-layer metal wiring for a one-chip layout held by a 4-input multiplexer inverter can be obtained.

REFERENCES:
patent: 5377136 (1994-12-01), Nishio et al.
patent: 5483083 (1996-01-01), Meguro et al.
patent: 5635737 (1997-06-01), Yin
patent: 5930163 (1999-07-01), Hara et al.
patent: 6307234 (2001-10-01), Ito et al.
patent: 6710371 (2004-03-01), Kitahara et al.
patent: 05-251671 (1993-09-01), None
patent: 2002-141477 (2002-05-01), None

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