LDMOS transistor structure using a drain ring with a...

Details LDMOS transistor structure using a drain ring with a... LDMOS transistor structure using a drain ring with a...

2002-02-20

2003-04-15

Whitehead, Jr., Carl (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

Having specific type of active device

C257S341000, C257S776000

Reexamination Certificate

active

06548839

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuit (IC) power management control devices and, in particular, to the utilization of a ring of drain contact around the outer periphery of a lateral DMOS (LDMOS) transistor array to improve the degradation of on-resistance with time due to hot electrons.
2. Discussion of the Related Art
As discussed by Brisbin, Strachan and Chaparala, “Hot-Carrier Reliability and Design of N-LDMOS Transistor Arrays”, 2001 IEEE International Integrated Reliability Workshop Final Report, Oct. 15-18, 2001, the increase in handheld and portable appliances operating in the 20-30V range has driven the need for IC power management control devices. These power management circuits typically combine high performance CMOS and bipolar transistors with a power MOS driver. The LDMOS is a common choice for the driver transistor. The above-cited Brisbin et al. publication is hereby incorporated by reference in its entirety to provide additional background information regarding the present invention.
LDMOS transistors are typically used at high currents and voltages, e.g., 24 V and 2 A/mm
2
. Under these conditions, hot electron effects occur, causing degradation of device parameters such as threshold voltage, gain and on-resistance, as discussed in detail in the above-cited Brisbin et al. publication. For LDMOS transistors, the parameter most susceptible to hot electron effects is the on-resistance.
As shown in
FIG. 1
, a conventional LDMOS array
100
is laid out as alternating source
102
and drain
104
regions formed in a semiconductor (e.g., silicon) substrate in a checkerboard pattern. All of the source regions
102
are connected in parallel, utilizing metal (e.g. Al) straps, as are all of the drain regions
104
, to form one large LDMOS transistor. The array
100
is typically surrounded by an isolation mechanism
106
such as trench isolation oxide, polyfill trench isolation or junction isolation. As stated above, the array is stressed under constant drain voltage and drain current conditions such as 24 V and 2 A/mm
2
. The time taken for the on-resistance to shift by a specified amount, e.g., 10%, is defined as the hot electron lifetime of the array.
SUMMARY OF THE INVENTION
The present invention provides an LDMOS transistor array architecture that significantly improves the hot electron lifetime of the device.
The improvement is due to the addition of a drain contact ring formed around the periphery of a conventional LDMOS transistor array. Utilization of the peripheral drain ring causes redistribution of the current flow within the LDMOS array, allowing safer operation at higher biases than with the conventional layout.


REFERENCES:
patent: 5355008 (1994-10-01), Moyer et al.
“Hot-Carrier Reliability and Design of N-LDMOS Transistor Arrays”; Douglas Brisbin, Andy Strachan, and Prasad Chaparala; National Semiconductor Corporation; pp. 19-23.

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