Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – Having specific type of active device
Reexamination Certificate
2001-01-24
2002-08-20
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
Having specific type of active device
C257S408000, C257S336000
Reexamination Certificate
active
06437377
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to computer chip manufacture, and more particularly to a structure and process that reduces sidewall capacitance between the gate and source/drain of a metal oxide semiconductor (MOS) device such as a metal oxide semiconductor field effect transistor (MOSFET).
2. Background Description
In MOSFETs, the total overlap capacitance is composed of both the inner and the outer fringing components. Prior to this invention, it was not recognized the critical role that the dielectric constant of the sidewall material plays in the output fringing overlap capacitance.
U.S. Pat. No. 5,627,097 to Venkatesan et al. describes a method of making a complementary metal oxide semiconductor (CMOS) device with reduced MOSFET parasitic capacitance between the substrate and source/drain. The Venkatesan et al. disclosure does not address gate to source/drain overlap capacitance.
U.S. Pat. No. 5,663,586 to Lin is specifically directed to the spacer construction in an FET. Lin contemplates a double spacer where the current drive is improved by using an additional conducting spacer. The Lin configuration; however, would increase the sidewall capacitance due to the presence of the additional spacer.
U.S. Pat. No. 5,102,816 to Manukonda et al. describes a method of forming a thin spacer adjacent to the gate sidewall with precise dimension control. However, the structure proposed in Manukonda et al. does not provide any advantages in terms of parasitic sidewall capacitance when compared to conventional designs.
U.S. Pat. No. 6,110,783 to Burr describes a method for forming a notched gate oxide asymmetric MOS device that potentially offers higher drive current than conventional devices. The notched structure is used to fabricate the asymmetric source/drain doping profile. Burr does not describe or suggest reducing sidewall capacitance.
Thus, while the level of skill in fabricating MOS devices is high, and the ability to control the formation of spacers, notch structures, and other aspects of the MOS device is well understood, prior to this invention little progress has been made in terms of identifying and reducing gate to source/drain overlap capacitance.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide structures for and methods of reducing gate to source/drain overlap capacitance in a MOSFET device.
According to the invention, there is a proportional relationship between the overlap capacitance for gate to source/drain in a MOSFET and the dielectric constant (k) of the material used in the sidewall spacer. This invention stems from the discovery that low k sidewall spacers can be used to reduce gate to source/drain capacitance. The total overlap capacitance is composed of the inner and outer fringing components. Usually, silicon nitride is used as the spacer, and silicon nitride has a k slightly higher than four (4). By replacing the silicon nitride spacer with a low-k material, the fringing component can be reduced. For example, if the low-k material has a k of 1, the fringing component can be reduced by a factor of 4 and this could potentially reduce the total overlap capacitance by 30%. However, low k materials are generally more fragile, and have more difficulty in holding their shape at higher temperatures. This would make using low k materials difficult to use in high temperature processing, upon exposure to silicide temperatures, and during normal thermal junction cycling (typically 1000 degrees C.).
The invention contemplates a notched gate filled with a low-k filler such as phosphorous doped low temperature oxide, SILK, fluorinated silicate glass (FSG), and other porous materials. In general, the low-k filler selected for this application should have a k of less than 3, it should not react with the gate material, and it should not decompose upon normal junction thermal cycling. Subsequently, the low-k filler can be encapsulated such that problems related to material compatibility with silicidation and problems related to whether the shape will hold up at high temperature are reduced. As an alternative embodiment, an air or gas filled cavity can be created under the notch. Due to the lack of a dielectric constant for air and other gases, this would give the lowest overlap capacitance possible in a CMOS technology.
REFERENCES:
patent: 5102816 (1992-04-01), Manukonda et al.
patent: 5627097 (1997-05-01), Venkatesan
patent: 5663586 (1997-09-01), Lin
patent: 5773331 (1998-06-01), Solomon et al.
patent: 5851890 (1998-12-01), Tsai et al.
patent: 6110783 (2000-08-01), Burr
patent: 6140192 (2000-10-01), Huang et al.
patent: 6218250 (2001-04-01), Hause et al.
patent: 6239472 (2001-05-01), Shenoy
patent: 020011135645 (2001-05-01), None
Ajmera Atul C.
Fung Ka Hing (Samuel)
Ku Victor
Schepis Dominic J.
Anderson Jay H.
Nelms David
Nguyen Thinh
Whitham, Curtis & Whitham, P.C.
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