Layout pattern of memory cell circuit

Details Layout pattern of memory cell circuit Layout pattern of memory cell circuit

1997-12-03

2000-03-28

Munson, Gene M.

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

Having specific type of active device

257369, 257401, 257903, H01L 2711, H01L 27118, H01L 27092

Patent

active

060435216

ABSTRACT:
A layout pattern of a memory cell circuit has a plurality of basic cells. Each basic cell has a small aspect ratio. Each basic cell has a NMOS transistor and a PMOS transistor. In the layout pattern, one basic cell is arranged in each row direction and the sixteen basic cells are arranged in each column direction.

REFERENCES:
patent: 5083178 (1992-01-01), Otsu
patent: 5422840 (1995-06-01), Naiki
patent: 5452245 (1995-09-01), Hickman et al.
patent: 5594270 (1997-01-01), Hiramoto et al.

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