Layout method of semiconductor device

Details Layout method of semiconductor device Layout method of semiconductor device

2005-03-29

2005-03-29

Nadav, Ori (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

Having specific type of active device

C257S202000, C257S204000, C257S390000, C257S394000, C257S401000

Reexamination Certificate

active

06872990

ABSTRACT:
A semiconductor device layout involving the following: arranging active regions of a plurality of transistors having at least more than one first and second electrodes disposed on a substrate; arranging a plurality of gates of transistors between more than one first and second electrodes of those active regions respectively by positioning at least more than one gates having predetermined width and length at a constant gap on the substrate; and arranging a plurality of dummy gates having predetermined width and length between a plurality of transistors (or between and outside transistors) at the same gap as that of the gates of transistors on the substrate, so that all the gates of transistors are arranged at a constant gap to minimize the variance of process deviations and accordingly reduce the difference of threshold voltage of transistors, thereby increasing reliability of the semiconductor device.

REFERENCES:
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patent: 5748035 (1998-05-01), Neugebauer
patent: 5923969 (1999-07-01), Oyamatsu
patent: 6020616 (2000-02-01), Bothra et al.
patent: 6174741 (2001-01-01), Hansch et al.
patent: 62-281444 (1987-12-01), None
patent: 7-147337 (1995-06-01), None
patent: 9-289251 (1997-11-01), None

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