Reduced inductance in ball grid array packages
Reduced stress LOC assembly including cantilevered leads
Reduced stress terminal pattern for integrated circuit devices a
Reduced stress under bump metallization structure
Reduced stress under bump metallization structure
Reduced temperature contact/via filling
Reduced variation in interconnect resistance using run-to-run co
Reduced-dimension microelectronic component assemblies with...
Reduced-dimension microelectronic component assemblies with...
Reducing layer separation and cracking in semiconductor devices
Reducing resistivity in interconnect structures by forming...
Reducing resistivity in interconnect structures of...
Reducing resistivity in interconnect structures of...
Reducing the migration of grain boundaries
Reduction of electromigration in dual damascene connector
Reduction of macro level stresses in copper/low-K wafers
Reduction of metal corrosion in semiconductor devices
Reduction of sector connecting line capacitance using...
Reduction of topside movement during temperature cycles
Redundant barrier structure for interconnect and wiring...