Reduced stress terminal pattern for integrated circuit devices a

Details Reduced stress terminal pattern for integrated circuit devices a Reduced stress terminal pattern for integrated circuit devices a

1994-08-31

1996-02-13

Limanek, Robert P.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Configuration or pattern of bonds

257779, 257666, H01L 2350

Patent

active

054913640

ABSTRACT:
A terminal pattern is provided for an integrated circuit device, such as a ball grid array package or an integrated circuit flip chip. The terminal pattern is composed of a number of terminals arranged in concentric arrays, each array having a substantially circular shape and being composed of a number of terminals. The terminal pattern is composed of at least two arrays, and more typically three or more arrays. When the integrated circuit device is mounted to its intended substrate, the individual terminals of the terminal pattern each register with and are soldered to a corresponding conductor of a conductor pattern formed on the substrate. A significant advantage is that, due to the terminals of the terminal pattern being arranged in concentric arrays, a smaller maximum width for the terminal pattern is achieved than possible with a conventional rectangular terminal pattern having the same number of terminals. As such, the terminal pattern and the resulting solder joints between the terminal pattern and its corresponding conductor pattern exhibit improved fatigue life as compared to the conventional rectangular terminal pattern.

REFERENCES:
patent: 3795845 (1974-03-01), Cass et al.

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