Reduced variation in interconnect resistance using run-to-run co

Details Reduced variation in interconnect resistance using run-to-run co Reduced variation in interconnect resistance using run-to-run co

1999-09-23

2000-12-05

Picardat, Kevin M.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

257773, 257774, 257784, H01L 214763

Patent

active

061570788

ABSTRACT:
A method, system, and memory storage medium for reducing variation of interconnect resistance of integrated circuits are provided. Interconnects are formed by a damascene process in which trenches are formed in an interlevel dielectric. The dimensions of the trenches are then measured. The dimension measurement results and the resistivity of the interconnect material are used to calculate a target thickness of interconnect material within the trench that gives a predetermined interconnect resistance. Interconnect material is then deposited within the trenches and upon the interlevel dielectric. A chemical-mechanical polishing process, which is used to remove interconnect material external to the trench, is then adjusted to leave the target thickness of interconnect material such that the completed interconnects have the predetermined resistance. Optionally, the resistance of the interconnects on the completed integrated circuits may be measured and compared to the predetermined interconnect resistance. Any observed deviations may then be used to further adjust the chemical-mechanical polishing process for subsequently fabricated integrated circuits.

REFERENCES:
patent: 5877037 (1999-03-01), O'Keefe et al.
patent: 6038383 (2000-03-01), Young et al.
patent: 6040240 (2000-03-01), Matsubara

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