Reduced stress under bump metallization structure

Details Reduced stress under bump metallization structure Reduced stress under bump metallization structure

2005-05-02

2008-09-02

Clark, Jasmine J (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S738000, C257S780000, C257S781000, C257S782000, C257S784000, C257SE21508, C257SE21627, C257SE21641

Reexamination Certificate

active

07420280

ABSTRACT:
An improved under bump structure for use in semiconductor devices is described. The under bump structure includes a passivation layer having a plurality of vias. The vias are positioned such that a plurality of vias are associated with (i.e., located over) each contact pad. A metal layer fills the vias and forms a metallization pad that is suitable for supporting a solder bump. Preferably the metal layer extends over at least portions of the passivation layer to form a unified under bump metallization pad over the associated contact pad. Each metallization pad is electrically connected to the contact pad through a plurality of the vias. The described under bump structures can be formed at the wafer level.

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patent: 2007/0273031 (2007-11-01), Lee et al.

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