Reduction of sector connecting line capacitance using...

Details Reduction of sector connecting line capacitance using... Reduction of sector connecting line capacitance using...

2001-12-11

2004-03-02

Pham, Hoai (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S906000

Reexamination Certificate

active

06700201

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
This invention relates generally to memory devices, and more particularly, to the connecting lines of a memory array having a plurality of sectors.
2. Background Art
FIG. 1
shows a general view of a memory device
20
in the form of an array having a plurality of sectors
22
A,
22
B,
22
C. Each sector
22
includes a plurality of bit lines B
1
, B
2
, . . . Bn (for example
1024
), and a plurality of word lines (for example
512
) orthogonal thereto (not shown), A plurality of sector connecting lines S
1
, S
2
, S
3
, . . . Sn connect the sectors
22
A,
22
B,
22
C (remaining structure left out for clarity in FIG.
1
). As shown in FIG.
1
and accompanying
FIG. 2
, which is a sectional view of
FIG. 1
, the bit lines B
1
-B
n
, (metal
1
) of each sector are parallel to each other and lie in a plane
24
. With reference to
FIG. 2
, the sector
22
includes a semiconductor substrate
26
having a plurality of drain regions
28
formed therein, with adjacent drain regions
28
separated by oxide regions
30
. A dielectric layer
32
is disposed thereover, and the bit lines B
1
-B
n
are formed in the dielectric layer
32
and connected to respective drain regions by vias V
1
, V
2
, . . . V
n
. Provided over this structure is another dielectric layer
34
, on which are provided the plurality of sector connecting lines S
1
, S
2
, . . . S
n
(metal
2
). These sector connecting lines S
1
-S
n
are parallel to the bit lines B
1
-B
n
, and lie in another plane
36
spaced from and parallel to the plane
24
of the bit lines B
1
-B
n
. Transistor switches T
1
, T
2
, . . . T
n
, connect each sector connecting line with either one of a pair of adjacent bit lines therebelow, all as is well-known.
The sector connecting lines, connecting many sectors of the array, are quite long. With device dimensions continuously decreasing, these sector connecting lines are brought closer and closer together, resulting in increased capacitance between the adjacent sector connecting lines. This high capacitance can affect the performance of the array, by slowing down operation and increasing the current demand thereof.
Therefore, what is needed is an improved layout of array which results in decreased capacitance between adjacent sector connecting lines.
DISCLOSURE OF THE INVENTION
In the present memory device, a plurality of sectors are included, each in turn including a plurality of parallel bit lines (metal
1
) which lie in a plane. Sector connecting lines, parallel to each other and to the bit lines, connect the sectors. The sector connecting lines include a first set of sector connecting lines (metal
2
) which lie in a plane parallel to and adjacent and spaced from the plane of the bit lines, and a second set of sector connecting lines (metal
3
) which lie in a plane parallel to and adjacent and spaced from the plane of the first set of sector connecting lines. When viewed across a sector, consecutive sector connecting lines lie in the two different planes thereof in alternating manner, i.e., in staggered relation. This staggered relation increases the distance between adjacent sector lines, so as to decrease capacitance therebetween.
The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. As will become readily apparent to those skilled in the art from the following description, there is shown and described an embodiment of this invention simply by way of the illustration of the best mode to carry out the invention. As will be realized, the invention is capable of other embodiments and its several details are capable of modifications and various obvious aspects, all without departing from the scope of the invention. Accordingly, the drawings and detailed description will be regarded as illustrative in nature and not as restrictive.


REFERENCES:
patent: 6265778 (2001-07-01), Tottori
patent: 6406968 (2002-06-01), Chien et al.

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