Reduction of macro level stresses in copper/low-K wafers

Details Reduction of macro level stresses in copper/low-K wafers Reduction of macro level stresses in copper/low-K wafers

2005-11-08

2011-12-13

Li, Meiya (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S734000, C257S751000, C257S774000, C257S775000, C257SE25029, C257SE25011, C257SE23073, C257SE23025, C257SE23024, C257SE23021, C257SE21508

Reexamination Certificate

active

08076779

ABSTRACT:
A pad structure and passivation scheme which reduces or eliminates IMC cracking in post wire bonded dies during Cu/Low-k BEOL processing. A thick 120 nm barrier layer can be provided between a 1.2 μm aluminum layer and copper. Another possibility is to effectively split up the barrier layer, where the aluminum layer is disposed between the two barrier layers. The barrier layers may be 60 nm while the aluminum layer which is disposed between the barrier layers may be 0.6 μm. Another possibility is provide an extra 0.6 μm aluminum layer on the top barrier layer. Still another possibility is to provide an extra barrier layer on the top-most aluminum layer, such that a top barrier layer of 60 nm is provided on a 0.6 μm aluminum layer, followed by another harrier layer of 60 nm, another aluminum layer of 0.6 μm and another barrier layer of 60 nm.

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