Reduction of topside movement during temperature cycles

Details Reduction of topside movement during temperature cycles Reduction of topside movement during temperature cycles

1999-09-13

2001-03-20

Potter, Roy (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

C257S620000, C257S700000

Reexamination Certificate

active

06204557

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the backend processing of integrated circuits. More specifically, the present invention relates to the processing of a topside film of an integrated circuit.
2. Discussion of Related Art
In general, an integrated circuit die has a topside film that is located over an uppermost metal layer. The purpose of the topside film is to protect the uppermost metal layer from damage. Typically, the topside film is a composite film that includes silicon oxide and silicon nitride.
FIG. 1
is a cross sectional diagram of an upper portion of an integrated circuit die
100
that includes silicon substrate
101
, intermediate interconnect structure
102
, uppermost metal layer
103
and topside film
104
. Intermediate interconnect structure
102
includes a plurality of conductive layers, insulating layers and contacts which are configured to route signals to and from circuit elements fabricated in substrate
101
. Topside film
104
is located over uppermost metal layer
103
. Topside film
104
includes a layer of silicon oxide
105
and an overlying layer of silicon nitride
106
. Silicon oxide layer
105
has a thickness on the order of 2000 Angstroms, and silicon nitride layer
106
has a thickness on the order of 8000 Angstroms. Topside film
104
exhibits a first thickness T
1
on the sides of uppermost metal layer
103
, and a second thickness T
2
over the top of uppermost metal layer
103
. The first thickness T
1
is thinner than the second thickness T
2
. For example, thickness T
1
is typically about 70 percent of thickness T
2
.
As illustrated in
FIG. 2
, when die
100
is put in a plastic package, plastic molding compound
200
covers the entire upper surface of die
100
. At this point, temperature cycling is commonly used to test the strength of topside film
104
. Temperature cycling refers to the process of cycling the packaged die between a low temperature (e.g., −65° C.) and a high temperature (e.g., 150° C.). Due to the different thermal expansion coefficients of plastic molding compound
200
and silicon substrate
101
, the molding compound
200
will apply a force on topside film
104
. This force is directed radially inward toward the center of die
100
at low temperatures, as indicated by arrow F
1
. If topside film
104
is not strong enough, topside film
104
will break around the sides of uppermost metal layer
103
as shown in FIG.
3
. The force exerted by molding compound
200
is greatest near the outer edge
201
of die
100
.
Solutions have been proposed to increase the strength of the topside film at the edges of the uppermost metal layer. One conventional solution is to form sidewall spacers on the sides of the uppermost metal layer prior to forming the topside film.
FIG. 4
is a cross sectional view of a die
400
that includes oxide spacers
401
formed on the sides of uppermost metal layer
103
. Because die
400
(
FIG. 4
) is similar to die
100
(FIG.
1
), similar elements in
FIGS. 1 and 4
are labeled with similar reference numbers. Silicon oxide layer
405
and silicon nitride layer
406
are formed over uppermost metal layer
103
and sidewall spacers
401
. The resulting topside film
404
has a thickness T
3
on the sides of uppermost metal layer
103
that is significantly greater than the thickness T
1
on the sides of uppermost metal layer
103
(FIG.
1
). As a result, topside film
404
is stronger than topside film
104
(FIG.
1
). However, the formation of sidewall spacers
401
significantly increases the complexity of the process used to create die
400
.
It would therefore be desirable to have a method and structure for increasing the width, and therefore the strength, of the topside film on the sides of an uppermost metal layer without increasing process complexity.
SUMMARY
Accordingly, the present invention provides an integrated circuit structure that includes a patterned uppermost conductive layer having a current-carrying trace. The current-carrying trace is connected to an underlying substrate by a multi-layer interconnect structure. The current-carrying trace, which is located around the outer edges of the integrated circuit structure, has at least one edge exhibiting a serpentine pattern. A topside film is located over the patterned uppermost conductive layer, wherein the topside film exhibits an increased thickness adjacent to the serpentine pattern. The increased thickness of the serpentine pattern results in a relatively strong topside film structure near the edges of the substrate. This strong topside film structure protects the topside film located over inner traces of the uppermost conductive layer during thermal cycling.
In one embodiment, the current-carrying trace is coupled to receive a V
SS
(ground) supply voltage. In another embodiment, the current-carrying trace is coupled to receive a V
CC
supply voltage.
In one variation, the patterned uppermost conductive layer further includes a surrounding trace located adjacent to an outer edge of the current-carrying trace. A serpentine gap is formed between the outer edge of the current-carrying trace, and the inner edge of the surrounding trace. In this variation, a portion of the topside film is located in the serpentine gap, thereby forming a serpentine wall of topside film. The serpentine wall can have different shapes. For example, the serpentine wall can exhibit outer angles of 120 degrees, thereby providing a honeycomb pattern to the serpentine wall. In this embodiment, the serpentine wall has a substantially uniform thickness along the axis of force applied during thermal cycling. In another embodiment, the serpentine wall has outer angles measuring about 90 degrees.
In accordance with another aspect of the invention, a plurality of openings are located through the current-carrying trace, whereby pillars of topside film are formed through the openings. The openings can have various shapes, including square. The patterned uppermost conductive layer can further include a plurality of traces located at corners of the substrate. A relatively rigid topside structure is provided around these traces.
In accordance with another embodiment of the present invention, the uppermost conductive layer additionally includes a second current-carrying trace located within the current-carrying trace. The second current-carrying trace has at least one edge with a serpentine pattern. The multi-layer interconnect structure provides a plurality of direct connections between the second current-carrying trace and selected circuit elements fabricated on the substrate.
The present invention will be more fully understood in view of the following description and drawings.


REFERENCES:
patent: 4364078 (1982-12-01), Smith et al.
patent: 5043793 (1991-08-01), Gootzen et al.
patent: 5266832 (1993-11-01), Yamamoto et al.
patent: 5317186 (1994-05-01), Wills et al.
patent: 5583370 (1996-12-01), Higgins, III et al.
patent: 5650666 (1997-07-01), Hartranft et al.
patent: 5831330 (1998-11-01), Chang
patent: 5834829 (1998-11-01), Dinkel et al.
patent: 5973387 (1999-10-01), Chen et al.

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