Dedicated redundancy circuits for different operations in a...
Dedicated redundancy circuits for different operations in a...
Deep pipe synchronous SRAM
Deep power down control circuit
Deep power down mode control circuit
Deep power down switch for memory device
Deep wordline trench to shield cross coupling between...
Deep wordline trench to shield cross coupling between...
Deep wordline trench to shield cross coupling between...
Default fuse condition for memory device after final test
Defect address storing circuit for semiconductor memory device
Defect avoidance in an integrated circuit
Defect management enabled PIRM and method
Defect management engine for generating a unified address to...
Defect management engine for semiconductor memories and memory s
Defect relief decision circuit with dual-fused clocked inverter
Defect tolerant scheme for a bubble lattice file
Defect tolerant self-testing self-repairing memory system
Defect-remediable semiconductor integrated circuit memory and sp
Defective address data storage circuit for nonvolatile...