Defect avoidance in an integrated circuit

Details Defect avoidance in an integrated circuit Defect avoidance in an integrated circuit

2001-10-03

2003-10-28

Le, Thong (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S201000, C365S230030

Reexamination Certificate

active

06639853

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a method of using an integrated circuit.
To make an integrated circuit containing a memory, a wafer is formed which contains a number of the integrated circuits. Typically, each wafer will contain between 10 and 1000 such integrated circuits. Integrated circuits containing a memory are generally relatively large compared to other types of integrated circuit. The larger the integrated circuit, the more likely it is that there will be a fault in the integrated circuit. Each integrated circuit contains a high number of devices. For example each integrated circuit may contain millions of devices. Faults are caused during the manufacturing process by dust or other contaminants. While the presence of contaminants during the manufacturing process can be reduced, it is impossible to completely eliminate their presence. A single fault in an integrated circuit may mean that the integrated circuit as a whole is regarded as being non functional and the integrated circuit is discarded. The large number of devices present on each integrated circuit means that the likelihood of at least one fault occurring on the integrated circuit may be relatively high and may be of the order of 50%.
If the yield, that is the number of functioning integrated circuits which can be obtained from a wafer, can be increased, the cost of each integrated circuit is reduced. For example if the yield can be increased from 50% to 90%, the cost savings can be very significant, particularly if a large number of the integrated circuits are required for a consumer product such as a mobile telephone.
Reference is made to U.S. Pat. No. 5,862,314 which addresses the problem of defects in a memory. A computer system is described which includes a memory requester that interfaces with a memory module. The memory module has memory portions. An error map is created and stored in the computer system. The error map identifies those memory portions which have defects. Using the error map, a remapping table is created and stored in the memory module. The remapping table is arranged to map each of the defective memory portions to a non defective memory portion in the memory module. If a request is received from a memory requester requesting access to a memory portion, a determination is made from the error map as to whether or not the requested memory portion is a defect portion or not. If the requested memory portion is a defect portion, then the remapping table is used to determine the memory portion which should now be accessed in response to the request.
This arrangement has the disadvantage that every time a request is made to the memory, a check must be made to see if the requested memory portion is a defect portion and if so the remapping table must be referred to. Thus the memory must additionally store the error table and the remapping table. The operation to access a given memory location may thus take an increased number of cycles.
SUMMARY OF THE INVENTION
It is an aim of embodiments of the present invention to address the problem discussed above.
According to a first aspect of the present invention there is provided a method of using an integrated circuit with at least one defect, said method comprising the steps of determining the location of one or more defects in said integrated circuit; selecting a program to be stored on said integrated circuit, said program being selected on the basis of the location of said one or more defects; and loading said program onto said integrated circuit.
According to a second aspect of the present invention there is provided a method of producing a plurality of integrated circuit devices, wherein each integrated circuit is produced in accordance with the method as set forth above, wherein the function of program stored on each integrated circuit is the same with memory addressing taking into account the location of said defects.


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