Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1982-02-02
1985-04-30
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
Bad bit
365210, G11C 1140
Patent
active
045148309
ABSTRACT:
An LSI memory comprises a memory array including usual memory cells arranged in a matrix form, usual address transistors for selecting usual lines connected to the columns or rows of the memory array, address lines for controlling the usual address transistors, spare memory cells provided in the memory array, a spare line connected to the spare memory cells, spare address transistors connected between the address lines and the spare lines, and nonvolatile memory elements connected between the sources of the spare address transistors and the ground. By putting any one of the nonvolatile memory elements into the written state, any one of the spare address transistors are conditioned into an active state so that the spare line can be substituted for a defective usual line.
REFERENCES:
patent: 4358833 (1982-11-01), Folmsbee et al.
patent: 4422161 (1983-12-01), Kressel et al.
Steiner, "Module Level Redundancy", IBM Tech. Disc. Bul., vol. 20, No. 7, 12/77, pp. 2594-2595.
Fitzgerald et al., "Semiconductor Memory Redundancy at the Module Level", IBM Tech. Disc. Bul., vol. 23, No. 8, 1/81, pp. 3601-3602.
Hagiwara Takaaki
Horiuchi Masatada
Kondo Ryuji
Minami Shin-ichi
Yatsuda Yuji
Fears Terrell W.
Hitachi , Ltd.
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