Defect address storing circuit for semiconductor memory device

Details Defect address storing circuit for semiconductor memory device Defect address storing circuit for semiconductor memory device

2007-11-27

2007-11-27

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Having fuse element

C365S200000

Reexamination Certificate

active

11319282

ABSTRACT:
A defect address storing circuit for a semiconductor memory device comprises a plurality of fuse pairs formed in a fuse region and a plurality of transistors formed in a transistor region outside the fuse region. The plurality of fuse pairs and the plurality of transistor pairs are arranged to form a continuous current path through at least one fuse in each of the plurality of fuse pairs, and through at least one transistor in each of the plurality of transistor pairs.

REFERENCES:
patent: 4922920 (1990-05-01), Thie et al.
patent: 5862087 (1999-01-01), Lee
patent: 6545920 (2003-04-01), Lee et al.
patent: 7075848 (2006-07-01), Choi et al.
patent: 2003/0026147 (2003-02-01), Bang et al.
patent: 11-162190 (1999-06-01), None
patent: 100183847 (1998-12-01), None
patent: 100207512 (1999-04-01), None
patent: 1020000066270 (2000-11-01), None
patent: 1020020039743 (2002-05-01), None

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