Defect relief decision circuit with dual-fused clocked inverter

Details Defect relief decision circuit with dual-fused clocked inverter Defect relief decision circuit with dual-fused clocked inverter

1996-08-29

1997-12-09

Clawson, Jr., Joseph E.

Static information storage and retrieval

Read/write circuit

Bad bit

3652257, 365233, 36523006, G11C 700, G11C 1714

Patent

active

056967233

ABSTRACT:
Disclosed is a defect relief decision circuit which has: a selection circuit for deciding either of a normal memory cell and a redundant memory cell to be used by cutting a fuse; a first programming fuse circuit which is controlled by the output of the selection circuit and to which an address bit of an address signal is input; a plurality of second programming fuse circuits which is controlled by the output of the selection circuit and to which an address bit different from the address bit of the address signal is input; and a logical circuit to which the outputs of the first and second programming fuse circuits are input and which decides to perform a defect relief operation when these coincide.

REFERENCES:
patent: 5325323 (1994-06-01), Nizaka
patent: 5373471 (1994-12-01), Saeki et al.
patent: 5406520 (1995-04-01), Tay
patent: 5426614 (1995-06-01), Harvard
patent: 5457656 (1995-10-01), Fu
patent: 5469391 (1995-11-01), Haraguchi

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