Defect tolerant self-testing self-repairing memory system

Details Defect tolerant self-testing self-repairing memory system Defect tolerant self-testing self-repairing memory system

1989-07-10

1990-07-03

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

Bad bit

365201, 371 81, 371 102, G11C 800

Patent

active

049396943

ABSTRACT:
A self-testing and self-repairing memory system is presented as well as a method for using it and a method for making it. This memory system is constructed from memory chips that have passed an abbreviated wafer probe test. After the memory system is assembled, it tests itself to locate defective memory cells. The memory system may decide to correct these defective memory cells or it may decide to correct them using an error correction code engine. This memory system tests itself during field use to locate defective memory cells. Once these defective memory cells are located, the memory system uses the error correction code engine to correct these defective memory cells. When the error correction code engine becomes overburdened with defective memory cells, then the memory system replaces these defective memory cells.

REFERENCES:
patent: 4493075 (1985-01-01), Anderson et al.
patent: 4707810 (1987-11-01), Ferrant

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