Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2000-06-13
2001-03-06
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S200000, C365S201000
Reexamination Certificate
active
06198659
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device having a redundant function of relieving a defective portion inside a memory cell array by substituting a reserved or relief portion (redundancy) for the defective portion, and in particular, to an address data storage circuit incorporated in such a nonvolatile semiconductor memory device for storing the address data of the defective portion and a method of writing the address data of the defective portion to the storage circuit.
In connection with nonvolatile semiconductor memory devices, there is a known method for replacing defective bit lines, defective word lines and defective memory cells with reserved ones (redundancy) to increase the yield. In the nonvolatile semiconductor memory device utilizing such a method, the addresses of the defective bit lines, the defective word lines and the defective memory cells, i.e., the defective address data are required to be stored.
Conventionally, methods for storing the defective address data typically employ a fuse, as disclosed in, for example, the Japanese Patent Laid-Open Publication No. HEI 6-150689.
FIG. 9
shows one example of a defective address data storage circuit employing a fuse. This figure shows the case where 3-bit address data is stored.
In this circuit, assuming that the address of the defective bit is
101
, then the second fuse F
1
is cut. Identification of the defective bit (defective address) and cutting of the fuse are performed during the device test.
Reference is next made to the case where the device actually operates after the completion of the test. If a power voltage Vcc rises, then a signal rdcamen comes to have a “high” level, and a transistor Tr that receives this signal as an input to its gate is turned on. In this stage, the first fuse F
0
and the third fuse F
2
are each conductive. Therefore, a voltage Vss is supplied to the inputs of the corresponding inverters In
0
and In
2
, and output terminals radd
0
and radd
2
of the inverters come to have a “high” level. On the other hand, with regard to an output signal from a terminal radd
1
, because the fuse F
1
has been cut, the input of the corresponding inverter In
1
is provided with a voltage of Vcc via a capacitor C, and the output comes to have a “low” level. The corresponding p-channel MOS transistor P is turned on, so that the “low” level is latched. Consequently, data of
101
is output from the output terminals radd
0
through radd
2
.
The most serious problem of this method is the layout area of the fuse portions. In accordance with the increase in integration density and the consequent increase in number of addresses to be stored, the layout area of these portions is inevitably increased. Therefore, the area is required to be reduced.
As a measure for solving this problem, there is a method of employing an electrically programmable nonvolatile semiconductor memory device in place of the fuse, as disclosed in, for example, the Japanese Patent Laid-Open Publication No. HEI 5-276018.
FIG. 10
shows a circuit diagram of an example for storing a 3-bit address employing this method. As is apparent from
FIG. 10
, nonvolatile semiconductor memory cells M
0
through M
2
having electrically erasable programmable floating gates are arranged in place of the fuses shown in FIG.
9
. In this case, instead of the cutting of the fuses, programming of the nonvolatile semiconductor memory cells is required. For this reason, a column decoder (not shown) for selectively turning on transfer gates Tr
0
, Tr
1
and Tr
2
by bit line selection signals bitse
10
, bitse
11
and bitse
12
, a data latch circuit LAT for writing defective address data and a level shifter HV are added to the circuit.
Reference is then made to the case where the address
101
is stored into this circuit. The circuit shown in
FIG. 10
is adapted for a flash memory which is programmed by means of channel hot electrons, as represented by ETOX (EPROM Thin Oxide). In the flash memory of this type, the threshold value of the memory cell in the initial state is about 1 V to 2 V.
The programming, or writing is performed by using channel hot electrons. A defective address is serially output to a data line DL in FIG.
10
. First, a “high” level signal corresponding to the first “1” of the defective address
101
is output to the data line DL. This signal is inverted by the write data latch circuit LAT and latched. Then, a “low” level signal is supplied to the level shifter HV, and the level shifter HV outputs 0 V. As a result, the transfer gate Tr
3
is turned off.
On the other hand, a voltage Vpp (10 V, for example) is applied to a word line WL of the memory cells. Then, to write to the memory cell M
0
, the signal bitse
10
of the voltage Vpp is applied to the transfer gate Tr
0
. Therefore, the transfer gate Tr
0
is turned on. However, the foregoing transfer gate Tr
3
is off, and therefore, the bit line BL
0
is placed in a floating state. Therefore, no programming is performed in the memory cell M
0
, and the threshold value of the memory cell M
0
remains in a low state (not higher than 2 V). In this stage, the bit lines BL
1
and BL
2
are also in the floating state.
In accordance with the next timing, a “low” level signal corresponding to “0” of the defective address
101
is output to the data line DL. Also, the signal bitse
11
of the voltage Vpp is applied to the transfer gate Tr
1
, and accordingly, the transfer gate Tr
1
is turned on. A “high” level (Vpp level) signal is output from the level shifter HV. Therefore, the transfer gate Tr
3
is turned on to output a voltage hhprg (6 V, for example) to the bit line BL
1
. In this stage, the bit lines BL
0
and BL
2
are in the floating state. On the other hand, the voltage Vpp is applied to the word line WL. Therefore, programming of the memory cell M
1
is performed by channel hot electrons, increasing the threshold value.
Subsequently, data corresponding to the last “1” of the defective address
101
is stored into the memory cell M
2
. This operation is similar to the aforementioned operation on the memory cell M
0
. As a result, no programming, or writing, of the memory cell M
2
is performed, and the threshold value of the memory cell M
2
is maintained in a low state.
The identification of the defective address and the writing of the defective address data to a memory cell are performed during the device test, basically in the wafer test stage. The wafer test is performed for one chip not one time but several times, at least two times as a normal temperature test and a high temperature test. Then, writing of the defective address data in a manner as described above is performed every test, which means that the writing is performed at least two times, namely at the normal temperature test and the high temperature test. In addition, the normal temperature test, for example, includes several test items, and it is a normal practice to write the defective address data each time for each test item, rather than writing the data collectively after the completion of all the tests.
Generally, the aforementioned writing is performed to memory cells connected to one word line in order for data such as the defective address and the like to be output when the device power starts, as described hereinbelow.
Reference is next made to the operation when the device is actually used after the storage of the defective address data.
First, if the power voltage is applied to the device, then the signal rdcamen rises to Vcc (3 V, for example), and the transfer gate Tr that receives this signal at its gate is turned on. Further, the word line WL also rises to Vcc, so that the memory cells M
0
and M
2
having a low threshold value are turned on to pull the bit lines BL
0
and BL
2
to the Vss level. As a result, “high” level signals as inverted are output from the output terminals radd
0
and radd
2
.
On the other hand, the memory cell M
1
is not turned on since the threshold value of the memory cell M
1
has been increased. Therefore, upon tu
Morrison & Foerster / LLP
Nguyen Tan T.
Sharp Kabushiki Kaisha
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