Balanced bitcell design for a multi-port register file
Balanced load memory and method of operation
Balanced reference sensing circuit
Balanced resistance load type SRAM cell
Balanced sense amplifier control for open digit line...
Balanced sense amplifier control for open digit line...
Balanced sense amplifier control for open digit line...
Balanced sensing arrangement for flash EEPROM
Ballistic direct injection flash memory cell on strained...
Ballistic injection NROM flash memory
Ballistic injection NROM flash memory
Band-gap voltage reference
Band-gap voltage reference
Bandgap engineered split gate memory
Bandgap reference circuit
Bandgap voltage and temperature coefficient trimming algorithm
Bandgap voltage reference generator
Bank architecture for a non-volatile memory enabling simultaneou
Bank availability indications for memory device and method...
Bank based self refresh control apparatus in semiconductor...