Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1999-09-28
2001-10-02
Ho, Hoai V. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185200, C257S345000, C257S391000
Reexamination Certificate
active
06297990
ABSTRACT:
BACKGROUND AND SUMMARY OF THE INVENTION
The present invention relates to skewed reference circuits for floating-gate memories.
BACKGROUND: FLOATING-GATE MEMORIES
Memories which do not lose their contents when the power is disconnected are referred to as “nonvolatile.” The most common types of nonvolatile semiconductor memories are those which exploit the properties of a floating-gate transistor. Such a transistor differs from to a normal MOS transistor in that a dielectrically isolated floating gate is interposed between a control gate and the channel. (Thus, the two gates are capacitively coupled to each other and to the channel.) The lower gate is called a “floating” gate, because it is electrically isolated. By injecting charges into the floating gate, the effective threshold voltage of the MOS transistor (as seen from the upper gate) can be changed. By applying an appropriate voltage to the control gate, and observing whether the transistor turns on, the state of the cell (i.e. whether charge is stored on the floating gate) can be detected.
Since the transistors of a memory array will always be as small as possible, the currents which must be detected will be relatively small. The sense amplifiers for floating-gate memories are differential circuits, which monitor the current drawn by a selected cell as compared with a fraction of the current from a reference cell. The reference cell must provide an output, to the sense amplifier, which is intermediate between the two possible outputs of the selected cell. This is not easy to do, since the current output of the cell will vary with temperature, power supply voltage variation, and the age of the cell.
In EPROMs, a “one” is defined as the state in which the floating gate memory cell conducts at a low threshold voltage Vt if the cell is “erased,” i.e. there are no excess elections in the floating gate. A “zero” is the state in which the threshold voltage Vt of the memory cell is raised (programmed) such that the cell does not conduct under normal operating conditions. The source-drain path conducts at a relatively high threshold voltage Vt if the cell is “programmed”, i.e. there are a sufficient number of electrons trapped on the floating gate to deplete the number of conductors in the source-drain path.
The margin between the threshold voltages Vt of erased memory cells and of programmed memory cells must be such that erased cells have threshold voltages Vt above a reference value and programmed cells have threshold voltages Vt below a reference accomplished by comparing the selected memory cell to a reference cell in such a way that the reference cell defines a condition, current or voltage, that resides between the “one” and “zero” state of the selected but. Both the reference cell and the selected cell have the same voltage Vcc applied to their control gates during read operations. The comparison to determine whether a “one” or a “zero” is stored on the selected cell is performed by a sense amplifier.
One previous method for improving the sensing capability of sense amplifiers includes changing the width of the load resistor/transistor on the sense amplifier. In this method, the difference between the current in the reference memory cell and in the selected memory cell is the same throughout the range from low control gate voltage Vcc to high control gate voltage Vcc.
According to a method described in U.S. Pat. No. 5,287,315 to Schreck et al., which is hereby incorporated by reference, an improvement in sense margins for both “ones” at a low control gate voltage Vcc and for “zeros” at a high control gate voltage Vcc may also be accomplished by forming the channel length of the reference memory cell to have a longer channel length than the memory cells of the array. This causes the reference memory cell to conduct much less current than the selected memory cell at low values of the control gate voltage Vcc. Because the threshold voltage Vt changes with the channel length, the sense amplifier response characteristic is skewed.
To further increase the margin between threshold voltages Vt of programmed and erased cells, the control gate of the reference cell is kept at the same potential as the control gate of the selected memory cell. As the control gate potential of both cells increases, the current of both the reference and memory cells increases. As the gate potential is elevated above a selected cell's programmed threshold voltage Vt such that the cell is conducting, the reference cell's current also increases, so that the gate potential must be raised well beyond the selected cell's threshold voltage Vt before the cell is detected as erased. Threshold Voltage (or “Vt”) is simply difference that distinguishes a one from a zero. It requires a gap between the lowest voltage that can be considered a “0” and the highest voltage that can be considered a “1”. In Schreck, the spread, or gap, between voltage high and voltage low of the channeled device is spread. A change in spread creates a change in margin of error.
Switches in use today are fast and will sense very quickly. It is advantageous to push the bit “low” response as low possible without failing. It is also advantageous to push the bit “high” response as high as possible.
FLOATING-GATE MEMORY SENSING WITH IMPROVED MARGIN
The present application discloses nonvolatile memories with improved sense margins. In particular, this invention relates to skewing of the characteristics of a sense amplifier by forming the reference memory cell and the individual memory cells with different device characteristics, especially channel doping levels.
Advantages of the disclosed methods and structures, in various embodiments, include better margin over temperature, process variation, aging, and/or power supply variation, for sensing.
REFERENCES:
patent: 5287315 (1994-02-01), Scherect et al.
patent: 5936888 (1999-08-01), Sugawara
patent: 5973957 (1999-10-01), Tedrow
Coffman Tim
Harris George E.
Brady III Wade James
Ho Hoai V.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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