Bank architecture for a non-volatile memory enabling simultaneou

Details Bank architecture for a non-volatile memory enabling simultaneou Bank architecture for a non-volatile memory enabling simultaneou

1996-12-20

1999-02-02

Robertson, David L.

Static information storage and retrieval

Read/write circuit

Simultaneous operations

36518511, 36518909, 36518533, 327530, G06F 1200, G11C 700

Patent

active

058674306

ABSTRACT:
A flash memory device is divided into two or more banks. Each bank includes a number of sectors. Each sector includes flash memory cells. Each bank has a decoder that selectively receives an address from an input address buffer or from an internal address sequencer controlled by an internal state machine. The output data for each bank can be communicated to a read sense amplifier or a verify sense amplifier. The read sense amplifier connects to the output buffer while the verify sense amplifier connects to the state machine. When one bank receives a write command, the internal state machine takes control and starts the program or erase operation. While one bank is busy with a program or erase operation, the other bank can be accessed for a read operation. Power is supplied for each of the read and write operations via an internal multiplexed multi power supply source that provides an amount of power needed based on the memory operation being performed.

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Atmel, 4 Megabit 2.7-volt Battery-Voltage.TM. Flash with 256 K EEPROM CMOS Combination Memory-AT29BV432 AWAKE.TM. Memory Architecture.
Atmel, 4 Megabit 5-volt Flash with 256K E.sup.2 PROM Memory-AT29C432 ConcurrentFlash .TM.

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