Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing
Reexamination Certificate
2004-02-11
2004-11-09
Lam, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Flip-flop used for sensing
C365S207000, C365S208000
Reexamination Certificate
active
06816425
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor memory devices and, more particularly, to an open digit line architecture memory device having a balanced sense amplifier control.
2. Description of the Related Art
An increasing number of electronic equipment and electronic-based systems require some form of high-speed memory devices for storing and retrieving information (or “data”). While the types of such memory devices vary widely, semiconductor memory devices are most commonly used in memory applications requiring implementation in a relatively small area. Within this class of semiconductor memory devices, the DRAM (Dynamic Random Access Memory) is one of the more commonly used types.
The DRAM has memory arrays consisting of a number of intersecting row and column lines of individual transistors or memory cells. In a conventional dynamic random access memory (DRAM) device each memory cell, or memory bit, consists of one transistor and one capacitor. A terminal of the transistor is connected to a digit line, or bitline, of the memory device. Another terminal of the transistor is connected to a terminal of the capacitor and the gate terminal of the transistor is connected to a wordline of the memory device. The transistor thus acts as a gate between the digit line and the capacitor.
The second terminal of the capacitor is connected to a voltage rail which carries a voltage, such as VCC/2. Thus, when the wordline for a particular cell is active, the gate transistor is in a conducting state and the capacitor is connected to the digit line. The capacitor stores a charge that, depending on whether the polarity of the voltage across the capacitor is positive or negative, represents either a logic high or a logic low value.
Typically, a microcomputer circuit selects (or activates) particular row and column lines to access selected memory cells. “Access” typically refers to reading data from or writing data to selected memory cells. Reading data from the memory cells involves the use of a sense amplifier to detect whether the voltage level stored in the memory cell represents a binary one or a binary zero.
Memory devices are typically constructed with complementary digit lines of equal capacitance. Sense amplifiers are connected between the digit lines and operate to sense the differential voltage across the digit lines. An open digit line architecture, as illustrated in
FIG. 1
, features the sense amplifier circuits
10
between arrays
12
,
14
,
16
,
18
. True and complement digit lines, such as for example D
1
20
and D
1
*
22
come from separate arrays
14
,
16
on each side of the sense amplifiers
10
as illustrated in FIG.
1
.
Operation of the sense amplifiers
10
is accomplished by applying various signals to each sense amplifier to fire the sense amplifiers as is well known in the art.
FIG. 2
illustrates the circuitry of a sense amplifier
10
of FIG.
1
. As is generally known in the art, the term sense amplifier includes a collection of circuit elements connected to the digit lines of a DRAM array. This collection typically includes devices for equilibration and bias, one or more N-sense amplifiers, one or more P-sense amplifiers, and devices connecting selected digit lines to input/output signal lines as will be described below.
As shown in
FIG. 2
, sense amplifier
10
includes a P-sense amplifier
30
and an N-sense amplifier
40
for sensing charge stored in the selected memory cell of the selected array via a voltage differential on the pair of digit lines D
1
20
and D
1
*
22
. Equilibration circuit
50
is provided to equilibrate the digit lines D
1
20
and D
1
*
22
. Equilibration circuit
50
includes transistor
52
with a first source/drain region coupled to digit line D
1
20
, a second source/drain region coupled to digit line D
1
*
22
and a gate coupled to receive an equilibration signal EQ. Equilibration circuit
50
further includes first and second transistors
54
and
56
. Transistor
54
includes a first source/drain region that is coupled to digit line D
1
20
, a gate that is coupled to receive the equilibration signal EQ and a second source/drain region that is coupled to receive an equilibration voltage Veq, which is typically equal to Vcc/2. Second transistor
56
includes a first source/drain region that is coupled to digit line D
1
*
22
, a gate that is coupled to receive the equilibration signal EQ and a second source/drain region that is coupled to the equilibration voltage Veq. When the signal EQ is at a high logic level, equilibration circuit
50
effectively shorts digit line D
1
20
to digit line D
1
*
22
such that both lines are equilibrated to the voltage Veq.
When P-sense amplifier
30
and N-sense amplifier
40
have sensed the differential voltage across the digit lines D
1
20
and D
1
*
22
(as described below), a signal representing the charge stored in the accessed memory cell is output from the DRAM device on the input/output (I/O) lines I/O
36
and I/O*
38
by connecting the I/O lines I/O
36
and I/O*
38
to the digit lines D
1
20
and D
1
*
22
, respectively. A column select (CSEL) signal is applied to transistors
40
,
42
to turn them on and connect the digit lines D
1
20
and D
1
*
22
to the I/O lines I/O
36
and I/O*
38
.
The operation of the P-sense amplifier
30
and N-sense amplifier
40
is as follows. These amplifiers work together to detect the access signal voltage and drive the digit lines D
1
20
and D
1
*
22
to Vcc and ground accordingly. As shown in
FIG. 2
, the N-sense amplifier
40
consists of cross-coupled NMOS transistors
42
,
44
and drives the low potential digit line to ground. Similarly, the P-sense amplifier
30
consists of cross-coupled PMOS transistors
32
,
34
and drives the high potential digit line to Vcc. The NMOS pair
42
,
44
or N-sense-amp common node is labeled RNL*. Similarly, the P-sense-amp
30
common node is labeled ACT (for ACTive pull-up). Initially, RNL* is biased to Vcc/2 and ACT is biased to ground. Since the digit line pair D
1
20
and D
1
*
22
are both initially at Vcc/2 volts, the N-sense-amp transistors
42
,
44
remain off due to zero Vgs potential. Similarly, both P-sense-amp transistors
32
,
34
remain off due to their positive Vgs potential. A signal voltage develops between the digit line pair
20
,
22
when the memory cell access occurs. While one digit line contains charge from the cell access, the other digit line serves as a reference for the sensing operation. The sense amplifier firing generally occurs sequentially rather than concurrently. The N-sense-amp
40
fires first and the P-sense-amp 30 second. The N-sense amplifier is fired by providing a signal, labeled NSA to a transistor
46
connecting the common node of the N-sense amplifier to ground. Dropping the RNL*signal toward ground will fire the N-sense-amp
40
. As the voltage between RNL* and the digit lines approaches Vt, the NMOS transistor whose gate connection is to the higher voltage digit line will begin to conduct. Conduction results in the discharge of the low voltage digit line toward the RNL* voltage. Ultimately, RNL* will reach ground, bringing the digit line with it. Note that the other NMOS transistor will not conduct since its gate voltage derives from the low voltage digit line, which is discharging toward ground.
Shortly after the N-sense-amp
40
fires, ACT will be driven toward Vcc by applying a low signal PSA to PMOS transistor
48
, thus connecting the common node of the P-sense amplifier
30
to Vcc. This activates the P-sense-amp
30
that operates in a complementary fashion to the N-sense-amp
40
. With the low voltage digit line approaching ground, a strong signal exists to drive the appropriate PMOS transistor into conduction. This will charge the high voltage digit line toward Vcc, ultimately reaching Vcc. Since the memory bit transistor remains on during sensing, the memory bit capacitor will charge to the RNL* or ACT voltage level. The voltage, and hence charge, which the memory bit capacitor
Derner Scott J.
Graham Scot M.
Porter Stephen R.
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