Balanced sensing arrangement for flash EEPROM

Details Balanced sensing arrangement for flash EEPROM Balanced sensing arrangement for flash EEPROM

1999-08-03

2000-04-18

Tran, Andrew Q.

Static information storage and retrieval

Floating gate

Particular biasing

36518513, 3651852, 36518533, G11C 1606

Patent

active

060523085

ABSTRACT:
A balanced sensing scheme (300) for a "flash" electrically programmable and erasable read only memory (EEPROM) is disclosed. In a read operation, an upper memory cell bank (302a or 302b) and a corresponding lower memory cell bank (302c or 302d) are coupled to a sense amplifier bank (306). One of the memory cell banks provides data while the other functions as a balanced load. In the event the memory cell bank that is to function as the balanced load is in the process of being erased, an alternate memory cell bank is coupled to the sense amplifier bank (306) to provide an equivalent balanced load.

REFERENCES:
patent: 4415992 (1983-11-01), Adlhoch

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