Ballistic injection NROM flash memory

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185260, C365S185160

Reexamination Certificate

active

11345080

ABSTRACT:
A split NROM flash memory cell is comprised of source/drain regions in a substrate. The split nitride charge storage regions are insulated from the substrate by a first layer of oxide material and from a control gate by a second layer of oxide material. The nitride storage regions are isolated from each other by a depression in the control gate. In a vertical embodiment, the split nitride storage regions are separated by an oxide pillar. The cell is programmed by creating a positive charge on the nitride storage regions and biasing the drain region while grounding the source region. This creates a virtual source/drain region near the drain region such that the hot electrons are accelerated in the narrow pinched off region. The electrons become ballistic and are directly injected onto the nitride storage region that is adjacent to the pinched off channel region.

REFERENCES:
patent: 5930634 (1999-07-01), Hause et al.
patent: 5969383 (1999-10-01), Chang et al.
patent: 6133098 (2000-10-01), Ogura et al.
patent: 6248633 (2001-06-01), Ogura et al.
patent: 6359807 (2002-03-01), Ogura et al.
patent: 6366500 (2002-04-01), Ogura et al.
patent: 6406945 (2002-06-01), Lee et al.
patent: 6518126 (2003-02-01), Wu et al.
patent: 6542412 (2003-04-01), Ogura et al.
patent: 6580641 (2003-06-01), Wu et al.
patent: 6709934 (2004-03-01), Lee et al.
patent: 6891751 (2005-05-01), Mikolajick
patent: 6897517 (2005-05-01), Van Houdt et al.
P. Pavan, et al. “Flash Memory Cells-An Overview” Proceedings of the IEEE, vol. 85, No. 8, Aug. 1997 pp. 1248-1271.
D. Kim, et al. “A 2Gb NAND Flash Memory with 0.044 um2Cell Size using 90nm Flash Technology” IEEE IEDM, 2002, 4 pgs.
J. Choi, et al. “Highly Manufacturable 1 Gb NAND Flash Using 0.12 um Process Technology” IEEE IEDM, 2001, 4 pgs.
B. Eitan et al., “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Lett, vol. 21, No. 11, (Nov. 2000), pp. 543-545, Copyright 2000 IEEE.
E. Lusky, et al., “Characterization of Channel Hot Electron Injection by the Subthreshold Slope of NROM™ Device,” IEEE Electron Device Lett., vol. 22, No. 11, (Nov. 2001) pp. 556-558, Copyright 2001 IEEE.
E. Maayan et al., “A 512Mb NROM Flash Data Storage Memory with 8MB/s Data Rate” Dig. IEEE Int. Solid-State Circuits Conf., San Francisco, (Feb. 2002), pp. 1-8, Copyright Saifun Semiconductors Ltd. 2002.
Y. Shin, et al. “High Reliable SONOS-type NAND Flash Memory Cell with AI203for Top Oxide” Technology Development Team, Samsung Electronics Co., Ltd., pp. 58-59 2002.
S. Ogura, et al. “Low Voltage, Low Current, High Speed Program Step Gate Cell with Ballistic Direct Injection for EEPROM/Flash” Digest International Electron Devices Meeting, 1998, pp. 987-990.
T. Saito, et al. “Split Gate Cell with Phonon Assisted Ballistic CHE injection” VLSI Tech. Symp. Digest Technical Papers, 2000, pp. 126-127.
Y. Naveh, et al. “Modeling of 10nm-Scale Ballistic MOSFET'S” IEEE Electron Device Letters, vol. 21, No. 5, May 2000, pp. 242-244.

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