Load-less four-transistor memory cell with different gate...

Details Load-less four-transistor memory cell with different gate... Load-less four-transistor memory cell with different gate...

2001-06-27

2002-08-27

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S154000, C365S181000

Reexamination Certificate

active

06442062

ABSTRACT:

BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a load-less four-transistor memory cell and a method for fabricating the same. More particularly, the present invention relates to a memory cell in a semiconductor memory device which is capable of realizing a stable and high-speed memory cell operation, and which can be suitably used as a SRAM (Static Random Access Memory).
(b) Description of the Related Art
Semiconductor memory devices are generally classified into three types including DRAMs (Dynamic Random Access Memories), SRAMs, and ROMs (Read Only Memories).
In a DRAM, each memory cell is composed of two elements, i.e., a MIS (Metal Insulator Semiconductor) transistor, such as MOS (Metal Oxide Semiconductor) transistor, and a storage capacitor. Therefore, a DRAM has advantages such as a high degree of integration and a high cost performance.
A SRAM, on the other hand, has advantages such as a high operating speed and a lower power dissipation as compared to the DRAM. However, in a SRAM, each memory cell is typically composed of six transistors, or four transistors and two resistive loads. Thus, it has be considered that a SRAM is not suitable for realizing a high degree of integration due to such a large number of elements per memory cell.
Basically, a SRAM includes a flip flop circuit or latch circuit and a pair of access transistors connected to the flip flop circuit, and the flip flop circuit is typically a combination of two inverter circuits connected in a positive feed-back loop.
An inverter circuit can be obtained as either a combination of an N-channel MOS transistor (referred to as an “NMOS transistor”) and a P-channel MOS transistor (referred to as a “PMOS transistor”), or a combination of an NMOS transistor and a resistive load.
A memory cell of a SRAM including six transistors is called a “full-CMOS memory cell” because the transistors are CMOS transistors, and is called herein full-CMOS six-transistor memory cell. This type of SRAM is the largest among various types of SRAMs in terms of the area occupied by a single memory cell.
On the other hand, a memory cell of a SRAM including four transistors and two resistive loads uses MOS transistors while providing the resistive loads above the MOS transistors, thereby reducing the total area to be occupied by the six elements. Therefore, the area required for one memory cell is smaller than that of a six-transistor memory cell.
However, production of the memory cell having resistive loads, as compared to that of a six-transistor memory cell, requires additional fabrication steps for forming the resistive loads because the resistive loads are generally formed on a polycrystalline silicon film.
It is also necessary to connect those elements with one another, thereby complicating the structure of the memory cell. Moreover, it is believed that it is more difficult to realize a low-voltage operation by the memory cell having the resistive loads compared to the full-CMOS six-transistor memory cell due to a large time constant of the resistive loads.
In recent years, there is a particular demand in the market for a SRAM capable of operating at a lower source voltage, i.e., at a low power dissipation. Accordingly, full-CMOS memory cells are more widely used than the memory cells having resistive loads despite of their smaller chip area.
Recently, a SRAM using full-CMOS memory cells that only require four transistors and do not have any resistive load was if proposed in the art, as described in Japanese Patent Laid-Open Publication Nos. 7-302847 and 6-104405. This type of memory cell is called hereinafter load-less four-transistor memory cell (full-CMOS four transistor) memory cell, or simply four-transistor memory cell.
Such a load-less four-transistor memory cell includes a pair of drive transistors (NMOS transistors) and a pair of access transistors (PMOS transistors), wherein no load element is connected to the storage node of the drive transistor.
The structure and the operation of the conventional six-transistor memory cell and those of the conventional four-transistor memory cell will now be described in detail with reference to
FIGS. 1A
,
1
B,
2
A and
2
B.
FIGS. 1A and 1B
are circuit diagrams illustrating the full-CMOS six-transistor memory cell and the load-less four-transistor memory cell, respectively, and
FIGS. 2A and 2B
are diagrams illustrating the operations of the six-transistor memory cell and the four-transistor memory cell, respectively.
As illustrated in
FIG. 1A
, the six-transistor memory cell includes a total of six transistors, i.e., a pair of drive transistors N
11
and N
12
(NMOS transistors), a pair of load transistors P
11
and P
12
(PMOS transistors), and a pair of access transistors or transfer transistors N
13
and N
14
(NMOS transistors).
The six-transistor memory cell operates as follows during a data retaining operation or a standby mode. As illustrated in
FIG. 2A
, the drive transistor N
11
and the access transistor N
13
are OFF whereas the load transistor P
11
is ON to maintain the storage node
11
at a high level, after data “1” is written to the six-transistor memory cell.
In this state, if the load transistor P
11
were OFF, the storage node
11
gradually loses its charge, thereby lowering the potential thereof, due to a junction leakage current or a leakage current through the drive transistor N
11
. The potential of the storage node
11
is maintained at the high level due to the charge by a current flowing from the Vcc source line via the load transistor P
11
.
When the access transistor N
13
is turned ON following the state as described above, a current flows from the storage node
11
to the digit line D
11
, thereby allowing the stored data to be read out to the digit lines or signal lines.
Next, the configuration and the operation of the load-less four-transistor memory cell will be described. As illustrated in
FIG. 1B
, the load-less four-transistor memory cell includes a total of four transistors, i.e., a pair of drive transistors N
15
and N
16
(NMOS transistors), and a pair of access transistors P
13
and P
14
(PMOS transistors). A major difference between the load-less four-transistor memory cell and the six-transistor memory cell, beside the difference in the number of elements, is that the access transistors P
13
and P
14
of the load-less four-transistor memory cell are PMOS transistors and supplies leakage current therethrough.
More specifically, the load-less four-transistor memory cell operates as follows during a data retaining operation. As illustrated in
FIG. 2B
, the drive transistor N
15
and the access transistor P
13
are OFF when the storage node
13
is at a high level, i.e., after data “1” is written to the load-less four-transistor memory cell.
In this state, without the leakage current through the access transistor P
13
, as stated in the case of the six-transistor memory cell, the potential of the storage node
13
gradually decreases due to a junction leakage current or a leakage current through the drive transistor N
15
. While the load-less four-transistor memory cell has no dedicated load element for supplying a current to the storage node
13
, the OFF-current (or junction leakage current) of the access transistor P
13
flows to the storage node
13
to thereby compensate for the charge loss from the storage node
13
.
When the access transistor P
13
is turned ON after the state as described above, a current flows from the storage node
13
to the digit line D
13
, thereby allowing the stored data to be read out.
In order for the load-less four-transistor memory cell to operate, it is necessary that the OFF-current (leakage current) of the access transistor P
13
or P
14
(PMOS transistor) is greater than the OFF-current of the drive transistor N
15
or N
16
(NMOS transistor).
An advantage of the load-less four-transistor memory cell is that it eliminates the need for providing load elements that are generally connected to the storage nodes of the drive transistors, thereby simplifying t

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