Loadless NMOS four transistor SRAM cell

Details Loadless NMOS four transistor SRAM cell Loadless NMOS four transistor SRAM cell

2001-02-23

2002-08-13

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S156000, C365S189090, C365S185240

Reexamination Certificate

active

06434040

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of Invention
Invention relates to static random access memory (SRAM) and more particularly to negative channel metal oxide semiconductor (NMOS) SRAM memory cell.
2. Related Art
There is a continuing need for higher density memory cells that can be fabricated in a given semiconductor die area. SRAM memory cells differ from other types of memory devices because there is no need for refreshing the data stored in the device. The demand for higher memory continues; thus, there is a need for memory cell designs that requires less silicon area yet meet the requirements of power, data stability, and speed of input and output operations of current applications.
SUMMARY OF INVENTION
The present invention resides in loadless four-transistor memory cell architecture. The memory cell device comprise a word: line for receiving an activation signal, a first and a second access transistor for processing the activation signal from the word line, a first and a second drive transistor for storing a bit value, the first access transistor cross-coupled to the second drive transistor and the second access transistor cross-couple to the first drive transistor; and complimentary bit lines for transmitting the bit value during input or output operations. The first and second access transistors and the first and second drive transistors are NMOS transistors.
The semiconductor memory cell device maintains a stable data hold by utilizing a sub-threshold voltage to charge the word line, the sub-threshold voltage being higher than the low voltage reference of the memory cell device and lower than the threshold voltage of the NMOS transistors, the application of the sub-threshold voltage to the word line occurs during non-active and non-charging operations of the memory cell device. The memory cell does not require any load elements. The precharge time of sub-threshold voltage biased word line is longer than the active time during input/output operations.
The loadless four-transistor NMOS SRAM memory cell of the present invention requires a significantly smaller silicon area than prior art four-transistor CMOS SRAM memory cells.


REFERENCES:
patent: 5070482 (1991-12-01), Miyagi
patent: 5936892 (1999-08-01), Wendell
patent: 5986924 (1999-11-01), Yamada
patent: 6172899 (2000-01-01), Marr et al.
patent: 6044011 (2000-03-01), Marr et al.
patent: 6297624 (2000-10-01), Mitsui et al.
patent: 6301146 (2001-10-01), Ang et al.
patent: 2001/0000308 (2001-04-01), Marr
patent: 2002/0024863 (2002-02-01), Forbes

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