Loadless 4T SRAM cell with PMOS drivers

Details Loadless 4T SRAM cell with PMOS drivers Loadless 4T SRAM cell with PMOS drivers

2001-10-12

2004-05-04

Phan, Trong (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S156000

Reexamination Certificate

active

06731533

ABSTRACT:

FIELD OF THE INVENTION
The invention is generally related to the field of SRAM circuits and more specifically to a novel design methodology for achieving a loadless 4T SRAM cell.
BACKGROUND OF THE INVENTION
The rapid growth of high-speed communications and 3-D graphics have created a large demand for large-scale and high speed static-random-access-memories (SRAM). SRAMs are essential to reduce data processing time and minimize chip cost. In general four-transistor (4T) SRAM cells have dominated the stand-alone SRAM market because they require less area than six-transistor (6T) SRAM cells. However for on-chip storage 4T SRAMs have not been used because they need a complex process to form a load element and have poor stability at low voltage. Recently, a 4T SRAM cell was developed that was suitable for on-chip SRAM memory. A schematic diagram of the conventional 4T SRAM cell is shown in FIG.
1
. The cell comprises two NMOS drive transistors
60
and
70
and two PMOS transfer/load transistors
40
and
50
. The wordline
30
and the bitline
10
and bitline/
20
are connected to the PMOS transistors
40
and
50
as shown in the Figure. In operation assume that node
80
is charged high (i.e. logic 1) and node
90
charged low (i.e. logic 0). In standby mode wordline
30
and bitlines
10
and
20
are precharged to the supply voltage V
DD
. This turns off the PMOS transistors
40
and
50
and, because node
80
is high and node
90
is low, NMOS transistor
70
is off and NMOS transistor
60
is on. For the SRAM cell to maintain its memory state without a refresh cycle, the off-state current of PMOS transistor
40
, I
OFF-P
, has to be equal to the sum of the off-state current of NMOS transistor
70
, I
OFF-N
, and the gate leakage current of transistor
60
, I
GN
when V
go
is high enough to be stable. Simulated curves showing the relationship between these currents for a typical 4T SRAM cell as a function of temperature is shown in FIG.
2
. Here it is observed that both the NMOS off-state current (I
OFF-N
)
100
and the PMOS off-state current (I
OFF-P
)
110
decreases with decreasing temperature. However, the gate leakage current (I
GN
)
120
which is due to direct tunneling through the gate oxide is independent of temperature. Thus the sum of the gate leakage current
120
and the NMOS off-state current
100
becomes insensitive to changes in temperature in the temperature range where the gate leakage current dominates. In the instant case this occurs at about 40° C. as shown in FIG.
2
. Therefore the 4T SRAM cell used to obtain the curves of
FIG. 2
will be unable to maintain its memory state below about 40° C. (point x in
FIG. 2
) without a refresh operation such as a controlled lowering of the wordline voltage. The gate current leakage I
GN
is a function of gate oxide thickness and increases as the gate oxide thickness decreases. As the MOS device size is reduced the concurrent reduction in gate oxide thickness will result in an increase in the gate leakage current I
GN
. This increase in gate leakage current I
GN
implies that as device dimensions are reduced greater increase in the pass gate leakage, such as by lowering the wordline voltage will be necessary to enable the 4T SRAM cell to hold its memory state. In order to increase the leakage to the high side (small voltage across pass gate transistor) the leakage to the low side (large voltage across pass gate transistor) results in greatly increased current and reduced performance. There is therefore a need for a SRAM memory cell with reduced area and reduced gate leakage current.
SUMMARY OF THE INVENTION
The instant invention is a memory cell which operates over a wide range of temperatures. In particular the memory cell comprises: providing a PMOS drive transistor with a gate terminal, a first source/drain terminal, and a second source/drain terminal; providing a NMOS pass transistor with a gate terminal, a first source/drain terminal and a second source/drain terminal; connecting said first source/drain terminal of said NMOS pass transistor to a bitline; connecting said second source/drain terminal of said NMOS pass transistor to a first storage node; connecting said gate terminal of said NMOS pass transistor to a wordline; connecting said first source/drain terminal of said PMOS drive transistor to a supply voltage; connecting said second source/drain terminal of said PMOS drive transistor to said first storage node; connecting said gate terminal of said PMOS drive transistor to a second storage node; and wherein a current flowing through the source/drain terminals of the NMOS pass transistor is greater than a current flowing through the source/drain terminals of the PMOS drive transistor for the same voltages applied between the gate and source/drain terminals of the PMOS drive transistor and the gate and source/drain terminals of the NMOS pass transistor.


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patent: 5684735 (1997-11-01), Kim
patent: 6044011 (2000-03-01), Marr et al.
patent: 6172899 (2001-01-01), Marr et al.
patent: 6172901 (2001-01-01), Portacci
patent: 6442060 (2002-08-01), Leung et al.
Noda K., et al., “A 1 9&mgr;m2Loadless CMOS Four-Transistor SRAM Cell in a 0 18&mgr;m Logic Technology,” 1998 IEEE, pp. 643-646.
Noda K., “An Ultra-High-Density High-Speed Loadless Four-Transistor SRAM Macro with a Dual-Layered Twisted Bit-Line and a Triple-Well Shield,” 2000 IEEE Custom Intergrated Circuits Conference, pp. 283-296.
Takeda, Koichi, et al. “A 16Mb 400MHz Loadless CMOS Four-Transistor SRAM Macro,” 2000 IEEE International Solid-State Circuits Conference, Feb. 8, 2000, Digest of Technical Papers, pp. 264-265.
Masuoka, S. et al., “A 0.99&mgr;m2Loadless Four-Transistor SRAM Cell in 0.13&mgr;m Generation CMOS Technology,” IEEE 2000 Symposium on VLSI Technology, Digest of Technical Papers, pp. 164-165.

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