Latch-up prevention for memory cells

Details Latch-up prevention for memory cells Latch-up prevention for memory cells

2007-03-13

2007-03-13

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S154000

Reexamination Certificate

active

11216665

ABSTRACT:
An SRAM memory cell is provided having a pair of cross-coupled CMOS inverters. The sources of the pull-up transistors forming each of the CMOS inverters are coupled to VCCthrough parasitic resistance of the substrate in which each is formed. The source of the p-type pull-up transistor is therefore always at a potential less than or equal to the potential of the N-well such that the emitter-base junction of the parasitic PNP transistor cannot become forward biased and latch-up cannot occur.

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