Low leakage current SRAM array

Details Low leakage current SRAM array Low leakage current SRAM array

2001-03-05

2003-05-06

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S156000, C365S190000

Reexamination Certificate

active

06560139

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates to integrated circuits, and more particularly, to a SRAM array having reduced bitline leakage current.
BACKGROUND OF THE INVENTION
Metal oxide semiconductor (MOS) static random access memory (SRAM) arrays are comprised of an array of SRAM cells. The SRAM cells are read, erased, and written to by means of bitlines (BL) and wordlines (WL). In one common design, the SRAM cells consist of load elements in a flip-flop configuration, together with two select transistors.
FIG. 1
is a schematic circuit diagram of a six-transistor (6T) SRAM cell
101
that is commonly and widely used in SRAM memory arrays. The SRAM cell
101
is known in the art as a 6T SRAM cell. The SRAM cell
101
includes N-type MOS (NMOS) transistors N
1
and N
2
(hereinafter transistors N
1
and N
2
) coupled between V
SS
(typically ground) and nodes A and B, respectively. Nodes A and B are further coupled to V
DD
by pull-up P-type MOS (PMOS) transistors P
1
and P
2
(hereinafter transistors P
1
and P
2
), respectively. Node A is further coupled to the gates of transistors P
2
and N
2
and node B is similarly coupled to the gates of transistors P
1
and N
1
.
Information is stored in SRAM cell
101
in the form of voltage levels in the flip-flop formed by the two cross-coupled inverters formed by transistors P
1
, N
1
and P
2
, N
2
, respectively. In particular, when node A is at a logic low state (the voltage of node A being approximately equal to V
SS
), transistor P
2
is on (in a low resistance state or conducting) and transistor N
2
is off (in a high resistance state or non conducting). When transistor P
2
is on and transistor N
2
is off, node B is at a logic high state (the voltage of node B is pulled up to approximately V
DD
). Further, when node B is at a logic high state, transistor P
1
is off and transistor N
1
is on. When transistor P
1
is off and transistor N
1
is on, node A is at a logic low state (the voltage of node A is pulled down to approximately V
SS
). In this manner, SRAM cell
101
remains in a latched state.
Nodes A and B are further coupled to a “bitline” and a “bitline-not” by NMOS select transistors N
3
and N
4
(hereinafter transistors N
3
and N
4
), respectively. The gates of transistors N
3
and N
4
are coupled to a word line to enable read and write operations, as those skilled in the art will understand.
A read operation is performed by turning on the word line and allowing one side of the SRAM cell to start pulling down on one line of the bitline pair. For example, if node A is low and the word line is pulled high, then a current will flow through select transistor N
3
and transistor N
1
to ground or V
ss
.
When node A is low and the word line is low, the SRAM cell
101
has a leakage current
103
that flows from the bitline through the select transistor N
3
and transistor N
1
down to ground or V
ss
.
As the size of the SRAM cells decreases, the amount of read current produced by the SRAM cell also decreases, particularly as the supply voltage V
cc
is lowered as technology advances. As the amount of read current decreases, the leakage current becomes larger relative to the read current, thereby making it more difficult to accurately read the SRAM cell. Thus, it is desirable to lower the amount of leakage current from each SRAM cell.
One method of solving this problem is to reduce the number of SRAM cells per bitline, thereby reducing the overall amount of leakage current. However, this increases the amount of overhead devices such as sense amplifiers, column multiplexer circuitry, etc. for a given number of SRAM cells.
Another approach is to increase the channel length of the transistors in the SRAM cell. However, this increases the SRAM cell size. Furthermore, effect of this approach is limited, as the transistor devices get smaller.


REFERENCES:
patent: 4764897 (1988-08-01), Kameyama et al.
patent: 5257236 (1993-10-01), Sharp
patent: 5581500 (1996-12-01), D'Souza
patent: 5610870 (1997-03-01), Choi
patent: 5621693 (1997-04-01), Nakase
patent: 5986923 (1999-11-01), Zhang et al.
patent: 6172901 (2001-01-01), Portacci

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