Latch-up prevention for memory cells

Details Latch-up prevention for memory cells Latch-up prevention for memory cells

1998-03-20

1999-12-21

Mai, Son

Static information storage and retrieval

Systems using particular element

Flip-flop

365154, 257370, 257372, G11C 1100, H01L 2976

Patent

active

060057971

ABSTRACT:
An SRAM memory cell is provided having a pair of cross-coupled CMOS inverters. The sources of the pull-up transistors forming each of the CMOS inverters are coupled to V.sub.cc through parasitic resistance of the substrate in which each is formed. The source of the p-type pull-up transistor is therefore always at a potential less than or equal to the potential of the N-well such that the emitter-base junction of the parasitic PNP transistor cannot become forward biased and latch-up cannot occur.

REFERENCES:
patent: 5298782 (1994-03-01), Sundaresan
patent: 5721445 (1998-02-01), Singh et al.
patent: 5804477 (1998-09-01), Lien

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